2K x 16 Dual-Port Static RAM

Functional Description The CY7C133 and CY7C143 are high-speed CMOS 2K by 16 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C133 can be utilized as either a stand-alone 16-bit dual-port static RAM or as a master dual-port RAM in conjun

2K x 16 Dual-Port Static RAM

Functional Description The CY7C133 and CY7C143 are high-speed CMOS 2K by 16 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C133 can be utilized as either a stand-alone 16-bit dual-port static RAM or as a master dual-port RAM in conjun

2K x 16 Dual-Port Static RAM

Functional Description The CY7C133 and CY7C143 are high-speed CMOS 2K by 16 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C133 can be utilized as either a stand-alone 16-bit dual-port static RAM or as a master dual-port RAM in conjun

2K x 16 Dual-Port Static RAM

Functional Description The CY7C133 and CY7C143 are high-speed CMOS 2K by 16 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C133 can be utilized as either a stand-alone 16-bit dual-port static RAM or as a master dual-port RAM in conjun

64Kx32 Flow-Thru SRAM with NoBL??Architecture

Functional Description The CY7C1333 is a 3.3V, 64K by 32 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1333 is equipped with the advanced No Bus Latency™ (NoBL™) logic required t

64Kx32 Flow-Thru SRAM with NoBL??Architecture

Functional Description The CY7C1333 is a 3.3V, 64K by 32 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1333 is equipped with the advanced No Bus Latency™ (NoBL™) logic required t

2K x 16 Dual-Port Static RAM

Functional Description The CY7C133 and CY7C143 are high-speed CMOS 2K by 16 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C133 can be utilized as either a stand-alone 16-bit dual-port static RAM or as a master dual-port RAM in conjun

2K x 16 Dual-Port Static RAM

Functional Description The CY7C133 and CY7C143 are high-speed CMOS 2K by 16 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C133 can be utilized as either a stand-alone 16-bit dual-port static RAM or as a master dual-port RAM in conjun

64Kx32 Flow-Thru SRAM with NoBL??Architecture

Functional Description The CY7C1333 is a 3.3V, 64K by 32 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1333 is equipped with the advanced No Bus Latency™ (NoBL™) logic required t

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

2K x 16 Dual-Port Static RAM

Functional Description The CY7C133 and CY7C143 are high-speed CMOS 2K by 16 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C133 can be utilized as either a stand-alone 16-bit dual-port static RAM or as a master dual-port RAM in conjun

2K x 16 Dual-Port Static RAM

Functional Description The CY7C133 and CY7C143 are high-speed CMOS 2K by 16 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C133 can be utilized as either a stand-alone 16-bit dual-port static RAM or as a master dual-port RAM in conjun

2-Mbit (64K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1336F is a 65,536 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increme

2-Mbit (64K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1336F is a 65,536 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increme

2-Mbit (64K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1336H is a 64K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments

2-Mbit (64K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1336H is a 64K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments

2-Mbit (64K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1336H is a 64K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments

2-Mbit (64K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1336H is a 64K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments

2-Mbit (64K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1336H is a 64K x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338 is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338 is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338 is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338 is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338 is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

128K x 32 Synchronous-Flow-Through 3.3V Cache RAM

Functional Description The CY7C1338B is a 3.3V, 128K by 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mb (128K x 32) Flow-Through Sync SRAM

Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increm

4-Mbit (128K x 32) Flow-Through Sync SRAM

Features • 128K X 32 common I/O • 3.3V –5 and +10 core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectabl

4-Mbit (128K x 32) Flow-Through Sync SRAM

Features • 128K X 32 common I/O • 3.3V –5 and +10 core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectabl

4-Mbit (128K x 32) Flow-Through Sync SRAM

Features • 128K X 32 common I/O • 3.3V –5 and +10 core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectabl

4-Mbit (128K x 32) Flow-Through Sync SRAM

Features • 128K X 32 common I/O • 3.3V –5 and +10 core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectabl

4-Mbit (128K x 32) Flow-Through Sync SRAM

Features • 128K X 32 common I/O • 3.3V –5 and +10 core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectabl

4-Mbit (128K x 32) Flow-Through Sync SRAM

Features • 128K X 32 common I/O • 3.3V –5 and +10 core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectabl

4-Mbit (128K x 32) Flow-Through Sync SRAM

Features • 128K X 32 common I/O • 3.3V –5 and +10 core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectabl