2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

2-Mbit (64K x 32) Pipelined SRAM with NoBL™ Architecture

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

2-Mbit (64K x 32) Pipelined SRAM with NoBL??Architecture

Functional Description[1] The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency™ (NoBL™) logic requ

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 2MBIT PARALLEL 100TQFP 集成电路（IC） 存储器