14-Bit Configurable Registered Buffer for DDR2

General Description The ICSSSTUA32S869B is 14-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers optimized to drive the

14-Bit Configurable Registered Buffer for DDR2

Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97U877 • Ideal for DDR2 400, 533 and 667 Product Features: • 14-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • 50 mo

14-Bit Configurable Registered Buffer for DDR2

Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97U877 • Ideal for DDR2 400, 533 and 667 Product Features: • 14-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • 50 mo