1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

FEATURES: • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 340MHz • Very low skew: ≤40ps • Very low jitter: ≤40ps • 1.8V AVDD and 1.8V VDDQ • CMOS control signal input • Test mode en

1.8V PLL Differential 1:10 SDRAM Clock Driver

1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

FEATURES: • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 340MHz • Very low skew: ≤40ps • Very low jitter: ≤40ps • 1.8V AVDD and 1.8V VDDQ • CMOS control signal input • Test mode en

1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

FEATURES: • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 340MHz • Very low skew: ≤40ps • Very low jitter: ≤40ps • 1.8V AVDD and 1.8V VDDQ • CMOS control signal input • Test mode en

1.8V Phase Locked Loop Differential 1:10 SDRAM Clock Driver

封装/外壳：56-TFBGA 包装：托盘 描述：IC PLL CLK DVR SDRAM 56-CABGA 集成电路（IC） 应用特定时钟/定时

封装/外壳：40-VFQFN 裸露焊盘 包装：托盘 描述：IC PLL CLK DVR SDRAM 40-VFQFPN 集成电路（IC） 应用特定时钟/定时

1.8V PLL Differential 1:10 SDRAM Clock Driver

Precision Optically Isolated Digital Voltage Sensor

Features  Superior optical isolation and insulation  10-MHz internal clock  1-bit, second-order sigma-delta modulator  16 bits resolution no missing codes (10 bits ENOB)  76 dB typical SNR, 66 dB typical SNDR  ±10 mV maximum offset error at room temperature  8 μV/°C typical offset dr

NPN Silicon Darlington Transistors (High current gain Low collector-emitter saturation voltage

● High current gain ● Low collector-emitter saturation voltage ● Complementary types: BC 876, BC 878 BC 880 (PNP)

NYLON THRU-HOLE SPACER

文件：186.13 Kbytes Page：1 Pages

Axial Lead & Cartridge Fuses

文件：185.59 Kbytes Page：3 Pages

Motor speed and phase control

文件：375.7 Kbytes Page：3 Pages