2.5V PHASE LOCKED LOOP CLOCK DRIVER

FEATURES: • PLL clock driver for DDR (Double Data Rate) synchronous DRAM applications • Spread spectrum clock compatible • Operating frequency: 60MHz to 220MHz • Low jitter (cycle-to-cycle): ±50ps • Distributes one differential clock input to four differential clock outputs • Enters low po

封装/外壳：28-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK BUF DDR 220MHZ 1CIRC 集成电路（IC） 应用特定时钟/定时

封装/外壳：28-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK BUF DDR 220MHZ 1CIRC 集成电路（IC） 应用特定时钟/定时

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