3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications • Distributes one clock input to one bank of ten outputs • Output enable bank control • External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal • No external RC network require

3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

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3.3V Phase-Lock Loop Clock Driver Zero Delay Buffer

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC CLK DVR PLL ZDB 1:10 24TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC CLK DVR PLL ZDB 1:10 24TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

Lamps for Photolithography

Description PerkinElmer Optoelectronics is a leading manufacturer of mercury short arc lamps ranging in output power from 1000 to 8000 watts. These lamps are used in the production of printed circuit boards, liquid crystal displays and semiconductors. The HSH Series lamps are used worldwide in mi

Lamps for Photolithography

Description PerkinElmer Optoelectronics is a leading manufacturer of mercury short arc lamps ranging in output power from 1000 to 8000 watts. These lamps are used in the production of printed circuit boards, liquid crystal displays and semiconductors. The HSH Series lamps are used worldwide in mi

Silicon NPNTransistor High Frequency Video Output

Features: • High Gain Bandwidth Product: fT = 2GHz • High Current Capacity: IC = 500mA Applications: • High–Definition CRT Display Video Output • Wide–Band Amp

50-150 MHz 1:10 SDRAM clock driver

DESCRIPTION The PCK2510SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

50-150 MHz 1:10 SDRAM clock driver

DESCRIPTION The PCK2510S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The P