Cost-effective, High-performance 32-bit DSP

文件：369.92 Kbytes Page：23 Pages

32-bit Audio Decoder DSP Family

Differentiating from the legacy Cirrus multi-standard, multichannel decoders, this new CS485xx family is still based on the same high-performance 32-bit fixed point Digital Signal Processor core but instead is equipped with much less memory, tailoring it for more cost-effective applications associ

32-bit Audio Decoder DSP Family

Differentiating from the legacy Cirrus multi-standard, multichannel decoders, this new CS485xx family is still based on the same high-performance 32-bit fixed point Digital Signal Processor core but instead is equipped with much less memory, tailoring it for more cost-effective applications associ

Cost-effective, High-performance 32-bit DSP

文件：369.92 Kbytes Page：23 Pages

ESD保护20KV的RS-485收发器

ESD保护20KV的RS-485收发器

ESD保护20KV的RS-485收发器

Cost-effective, High-performance 32-bit DSP

文件：369.92 Kbytes Page：23 Pages

封装/外壳：48-LQFP 包装：卷带（TR） 描述：IC DSP HP 32BIT 4CH I/O 48LQFP 集成电路（IC） DSP（数字信号处理器）

封装/外壳：48-LQFP 包装：托盘 描述：IC DSP HP 32BIT 4CH I/O 48LQFP 集成电路（IC） DSP（数字信号处理器）

SWAGE/FORCE FIT STANDOFFS

[KEYSTONE] SWAGE/FORCE FIT STANDOFFS

Buffered, 4-Channel Simultaneous Sampling, 20-Bit 250kSPS DAS

FEATURES ► Complete 20-bit data acquisition system ► Simultaneous sampling of 4 internally buffered channels ► 250kSPS per channel throughput ► Differential, wide common-mode range inputs ► ±75pA typical input leakage at 25°C ► Full-scale input step settling time

Buffered, 4-Channel Simultaneous Sampling, 20-Bit 250kSPS DAS

FEATURES ► Complete 20-bit data acquisition system ► Simultaneous sampling of 4 internally buffered channels ► 250kSPS per channel throughput ► Differential, wide common-mode range inputs ► ±75pA typical input leakage at 25°C ► Full-scale input step settling time

5 V Slew-Rate Limited Half- and Full-Duplex RS-485/RS-422 Transceivers

GENERAL DESCRIPTION The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857 are differential line transceivers suitable for high speed half- and full-duplex data communication on multipoint bus transmission lines. They are designed for balanced data transmission and comply with EIA St

SWAGE/FORCE FIT STANDOFFS

文件：336.76 Kbytes Page：1 Pages