NPN Digital Silicon Transistor

FEATURE * Small surface mounting type. (SC-59/SOT-346) * High current gain. * Suitable for high packing density. * Low colloector-emitter saturation. * High saturation current capability. * Internal isolated NPN transistors in one package. * Built in bias resistor(R1=10kΩ, Typ. ) APPLICATI

NPN Digital Silicon Transistor

PNP SILICON BIAS RESISTOR TRANSISTOR

This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. The

Bias Resistor Transistor PNP Silicon Surface Mount Transistor with Monolithic Bias Resistor Network

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its xternal resistor bias network. The BRT eliminate

CASE 463-01, STYLE 1 SOT-416/SC-90

The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital transistors are designed to replace a single device and its external resistor bias network. The BRT eliminat

CASE 463-01, STYLE 1 SOT-416/SC-90

Bias Resistor Transistor NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. These digital trans

0.25關m Sea of Gates and Customer Structured Arrays

DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit (ASIC) products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MG115P series and the CSA-based MG75P series use a five-layer metal process on 0.25µm drawn (0.18µm L-eff