丝印代码：CDC536；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

丝印代码：CDC536；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

丝印代码：CDC536；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

丝印代码：CDC536；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

丝印代码：CDC536；3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

FEATURES · Low-Output Skew for Clock-Distribution and Clock-Generation Applications · Operates at 3.3-V VCC · Distributes One Clock Input to Six Outputs · One Select Input Configures Three Outputs to Operate at One-Half or Double the Input Frequency · No External RC Network Required · Ext

具有 1/2x、1x 和 2x 频率选项的 100MHz、3.3V PLL 时钟驱动器

The CDC536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular microprocessors ope • Low-Output Skew for Clock-Distribution and Clock-Generation Applications\n• Distributes One Clock Input to Six Outputs\n• No External RC Network Required\n• Application for Synchronous DRAM, High-Speed Microprocessor\n• TTL-Compatible Inputs and Outputs\n• State-of-the-Art EPIC-IIB™ BiCMOS Design ;

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：170.14 Kbytes Page：12 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：170.14 Kbytes Page：12 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：295.53 Kbytes Page：14 Pages

封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC 3.3V PLL CLOCK DRIVER 28-SSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：295.53 Kbytes Page：14 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：295.53 Kbytes Page：14 Pages

封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC 3.3V PLL CLOCK DRIVER 28-SSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：295.53 Kbytes Page：14 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：170.14 Kbytes Page：12 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：295.53 Kbytes Page：14 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

文件：295.53 Kbytes Page：14 Pages

Numeric Display

Numeric Display 3 Digit 14.4mm (.6”) Series

Numeric Display

文件：23.76 Kbytes Page：1 Pages

Numeric Display

文件：23.76 Kbytes Page：1 Pages

Numeric Display

文件：23.76 Kbytes Page：1 Pages

Numeric Display

文件：23.76 Kbytes Page：1 Pages