Dual 2-Bit Bistable Transparent Latch

Features • True and Complementary Outputs • Buffered Inputs and Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • B

Dual 2-Bit Bistable Transparent Latch

文件：348.92 Kbytes Page：15 Pages

Dual 2-Bit Bistable Transparent Latch

文件：430.25 Kbytes Page：19 Pages

Dual 2-Bit Bistable Transparent Latch

文件：508.01 Kbytes Page：17 Pages

Dual 2-Bit Bistable Transparent Latch

文件：56.59 Kbytes Page：8 Pages

Dual 2-Bit Bistable Transparent Latch

文件：348.92 Kbytes Page：15 Pages

Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

4 BIT D TYPE LATCH

DESCRIPTION TheM54/74HCT75 is a high speed CMOS4-BITD-TYPE LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. . HIGH SPEED tPD = 15 ns (TYP.) AT VCC = 5 V . LOW POWER DISSIPATION I

4 BIT D TYPE LATCH

DESCRIPTION The M74HCT75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED : tPD = 21ns (TYP.) at VCC = 4.5V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0