Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

Octal Schmitt trigger buffer/line driver; 3-state; inverting

GENERAL DESCRIPTION The 74HC/HCT7540 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inverting outputs • Schmitt trigger action on all data inputs • Output capab

Octal Schmitt trigger buffer/line driver; 3-state; inverting Rev. 4 ??31 December 2012

Octal Schmitt trigger buffer/line driver; 3-state; inverting

1. General description The 74HC7540; 74HCT7540 is an 8-bit inverting buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This

Octal Schmitt trigger buffer/line driver; 3-state; inverting

1. General description The 74HC7540; 74HCT7540 is an 8-bit inverting buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This

Octal Schmitt trigger buffer/line driver; 3-state; inverting Rev. 4 ??31 December 2012

Octal Schmitt trigger buffer/line driver; 3-state; inverting Rev. 4 ??31 December 2012

Octal Schmitt trigger buffer/line driver; 3-state

GENERAL DESCRIPTION The 74HC/HCT7541 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Non-inverting outputs • Schmitt trigger action on all data inputs • Output c

Octal Schmitt trigger buffer/line driver; 3-state

1. General description The 74HC7541; 74HCT7541 is an 8-bit buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables t

Octal Schmitt trigger buffer/line driver; 3-state

The 74HC7541; 74HCT7541 is an 8‑bit buffer/line driver with Schmitt‑trigger inputs and 3‑state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high‑impedance OFF‑state. Inputs include clamp diodes. This enables the use of current limiting r • Non-inverting outputs\n• Low-power dissipation\n• Input levels:• For 74HC7541: CMOS level\n• For 74HCT7541: TTL level\n\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °;

Octal Schmitt trigger buffer/line driver; 3-state

1. General description The 74HC7541; 74HCT7541 is an 8-bit buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables t

Octal Schmitt trigger buffer/line driver; 3-state

1. General description The 74HC7541-Q100; 74HCT7541-Q100 is an 8-bit buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that

Octal Schmitt trigger buffer/line driver; 3-state

The 74HC7541-Q100; 74HCT7541-Q100 is an 8-bit buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current li • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from ‑40 °C to +85 °C and from ‑40 °C to +125 °C\n\n• Non-inverting outputs\n• Low-power dissipation\n• Input levels:• For 74HC7541-Q100: CMOS level\n• For 74HCT7541-Q100: TTL level\n\n• Complies with JEDEC standard ;

Octal Schmitt trigger buffer/line driver; 3-state

The 74HC7541; 74HCT7541 is an 8‑bit buffer/line driver with Schmitt‑trigger inputs and 3‑state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high‑impedance OFF‑state. Inputs include clamp diodes. This enables the use of current limiting r • Non-inverting outputs\n• Low-power dissipation\n• Input levels:• For 74HC7541: CMOS level\n• For 74HCT7541: TTL level\n\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °;

Octal Schmitt trigger buffer/line driver; 3-state

1. General description The 74HC7541; 74HCT7541 is an 8-bit buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables t

Octal Schmitt trigger buffer/line driver; 3-state

1. General description The 74HC7541-Q100; 74HCT7541-Q100 is an 8-bit buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that

Octal Schmitt trigger buffer/line driver; 3-state

1. General description The 74HC7541-Q100; 74HCT7541-Q100 is an 8-bit buffer/line driver with Schmitt-trigger inputs and 3-state outputs. The device features two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that

8-bit shift register with input latches

GENERAL DESCRIPTION The 74HC/HCT7597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT7597 both consist of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit sh

Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC BUFFER INVERT 5.5V 20SO 集成电路（IC） 缓冲器，驱动器，接收器，收发器

封装/外壳：20-DIP（0.300"，7.62mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUFFER INVERT 5.5V 20DIP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Octal Schmitt trigger buffer/line driver; 3-state

Octal Schmitt trigger buffer/line driver; 3-state

文件：951.53 Kbytes Page：15 Pages

Octal Schmitt trigger buffer/line driver; 3-state

Octal Schmitt trigger buffer/line driver; 3-state

Octal Schmitt trigger buffer/line driver; 3-state

文件：951.53 Kbytes Page：15 Pages

4 BIT D TYPE LATCH

DESCRIPTION TheM54/74HCT75 is a high speed CMOS4-BITD-TYPE LATCH fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. . HIGH SPEED tPD = 15 ns (TYP.) AT VCC = 5 V . LOW POWER DISSIPATION I

4 BIT D TYPE LATCH

DESCRIPTION The M74HCT75 is an high speed CMOS 4 BIT D TYPE LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED : tPD = 21ns (TYP.) at VCC = 4.5V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0

Dual 2-Bit Bistable Transparent Latch

文件：56.59 Kbytes Page：8 Pages

Dual 2-Bit Bistable Transparent Latch

文件：348.92 Kbytes Page：15 Pages