丝印代码：CD74HCT74E；CDx4HCT74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip−fl

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip−fl

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip−fl

Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

High–Performance Silicon–Gate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be usedas a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip–flops with individual Set, Reset, and Clock inputs. Information a