High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features • Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237 • l/O Port or Memory Selector • Two Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25oC (CD74HC237) • Fanout (Over

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features • Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237 • l/O Port or Memory Selector • Two Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25oC (CD74HC237) • Fanout (Over

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features • Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237 • l/O Port or Memory Selector • Two Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25oC (CD74HC237) • Fanout (Over

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

文件：668.7 Kbytes Page：20 Pages

High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches

文件：65.95 Kbytes Page：9 Pages

封装/外壳：16-DIP（0.300"，7.62mm） 包装：管件 描述：IC DECODER/DEMUX 1X3:8 16DIP 集成电路（IC） 信号开关，多路复用器，解码器

High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches

文件：65.099 Kbytes Page：10 Pages

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

文件：381.06 Kbytes Page：16 Pages

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

文件：528.3 Kbytes Page：19 Pages

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

文件：1.00109 Mbytes Page：21 Pages

High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches

文件：65.099 Kbytes Page：10 Pages

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features • Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237 • l/O Port or Memory Selector • Two Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25oC (CD74HC237) • Fanout (Over

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

Features • Select One of Eight Data Outputs - Active Low for CD74HC137 and CD74HCT137 - Active High for ’HC237 and CD74HCT237 • l/O Port or Memory Selector • Two Enable Inputs to Simplify Cascading • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25oC (CD74HC237) • Fanout (Over

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

文件：1.00109 Mbytes Page：21 Pages

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

文件：528.3 Kbytes Page：19 Pages

3-to-8 line decoder/demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i

3-to-8 line decoder/demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i

3-to-8 line decoder/demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i

3-to-8 line decoder/demultiplexer with address latches

GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or i