High-Speed CMOS Logic Dual 2- to 4-Line Decoder/Demultiplexer

Features • Multifunction Capability - Binary to 1 of 4 Decoders or 1 to 4 Line Demultiplexer • Active Low Mutually Exclusive Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Load

High-Speed CMOS Logic Dual 2- to 4-Line Decoder/Demultiplexer

文件：415.07 Kbytes Page：13 Pages

High-Speed CMOS Logic Dual 2- to 4-Line Decoder/Demultiplexer

文件：271.15 Kbytes Page：11 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC DECODER/DEMUX 1X2:4 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

High-Speed CMOS Logic Dual 2- to 4-Line Decoder/Demultiplexer

文件：271.15 Kbytes Page：11 Pages

High-Speed CMOS Logic Dual 2- to 4-Line Decoder/Demultiplexer

文件：415.07 Kbytes Page：13 Pages

High-Speed CMOS Logic Dual 2- to 4-Line Decoder/Demultiplexer

文件：415.07 Kbytes Page：13 Pages

Dual 2-to-4 line decoder/demultiplexer

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-