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74HCT139D价格

参考价格:¥0.4435

型号:74HCT139D,652 品牌:NXP 备注:这里有74HCT139D多少钱,2026年最近7天走势,今日出价,今日竞价,74HCT139D批发/采购报价,74HCT139D行情走势销售排行榜,74HCT139D报价。
型号 功能描述 生产厂家 企业 LOGO 操作
74HCT139D

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

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74HCT139D

Dual 2-to-4 line decoder/demultiplexer

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74HCT139D

Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-

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74HCT139D

Dual 2-to-4 line decoder/demultiplexer

The 74HC139; 74HCT139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. • Input levels:• For 74HC139: CMOS level\n• For 74HCT139: TTL level\n\n• Demultiplexing capability\n• 2 independent 2-to-4 decoders\n• Multifunction capability\n• Suitable for memory decoding, data routing or code conversion\n• Complies with JEDEC standard no. 7A\n• Active LOW mutually exclusive out;

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Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

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Dual 2-to-4 line decoder/demultiplexer

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74HCT139DB-Q100 - Dual 2-to-4 line decoder/demultiplexer

Dual 2-to-4 line decoder/demultiplexer - The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the ·Automotive product qualification in accordance with AEC-Q100 (Grade 1)·Specified from ‑40 °C to +85 °C and from ‑40 °C to +125 °C;

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Dual 2-to-4 line decoder/demultiplexer

The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer ap • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from ‑40 °C to +85 °C and from ‑40 °C to +125 °C\n\n• Input levels:• For 74HC139-Q100: CMOS level\n• For 74HCT139-Q100: TTL level\n\n• Demultiplexing capability\n• 2 independent 2-to-4 decoders\n• Multifunction capab;

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Dual 2-to-4 line decoder/demultiplexer

1. General description The 74HC139-Q100; 74HCT139-Q100 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input f

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封装/外壳:16-SOIC(0.154",3.90mm 宽) 包装:管件 描述:IC DECODER/DEMUX 1 X 2:4 16SO 集成电路(IC) 信号开关,多路复用器,解码器

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封装/外壳:16-SSOP(0.209",5.30mm 宽) 包装:管件 描述:IC DECODER/DEMUX 1X2:4 16SSOP 集成电路(IC) 信号开关,多路复用器,解码器

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Dual 2-to-4 line decoder/demultiplexer

文件:762.31 Kbytes Page:18 Pages

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Dual 2-to-4 line decoder/demultiplexer

文件:762.31 Kbytes Page:18 Pages

NEXPERIA

安世

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

PHILIPS

飞利浦

Dual 2-to-4 line decoder/demultiplexer

GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent dec

PHILIPS

飞利浦

DUAL 2 TO 4 DECODER/DEMULTIPLEXER

文件:239.18 Kbytes Page:9 Pages

STMICROELECTRONICS

意法半导体

74HCT139D产品属性

  • 类型

    描述

  • VCC (V):

    4.5 - 5.5

  • Logic switching levels:

    TTL

  • Output drive capability (mA):

    ± 4

  • tpd (ns):

    16

  • Power dissipation considerations:

    low

  • Tamb (°C):

    -40~125

  • Rth(j-a) (K/W):

    92

  • Ψth(j-top) (K/W):

    9.3

  • Rth(j-c) (K/W):

    51

  • Package name:

    SO16

更新时间:2026-8-3 13:34:00
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