CDx4HCT11 Triple 3-Input AND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

具有 TTL 兼容型 CMOS 输入的 3 通道、3 输入、4.5V 至 5.5V 与门

This device contains three independent 3-input AND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. • LSTTL input logic compatible \n• CMOS input logic compatible \n• Buffered inputs\n• Wide operating temperature range: -55°C to +125°C\n• Significant power reduction compared to LSTTL logic ICs;

High Speed CMOS Logic Triple 3-Input AND Gate

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High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

丝印代码：CD74HCT112E；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

丝印代码：CD74HCT11E；CDx4HCT11 Triple 3-Input AND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：CD74HCT11E；CDx4HCT11 Triple 3-Input AND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：CD74HCT11E；CDx4HCT11 Triple 3-Input AND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：CD74HCT11E；CDx4HCT11 Triple 3-Input AND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

具有设置和复位端的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器

The ’HC112 and ’HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.\n\n These flip-flops have independent J, K, Set, Reset, a • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times\n• Complementary Outputs\n• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C\n• Standard Outputs . . . . . 10 LSTTL Loads\n• Wide Operating Temperature Range . . . –55°C to 125°C\n• Significant Pow;

CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

丝印代码：HCT11M；CDx4HCT11 Triple 3-Input AND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：HCT11M；CDx4HCT11 Triple 3-Input AND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：HCT11M；CDx4HCT11 Triple 3-Input AND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：HCT11M；CDx4HCT11 Triple 3-Input AND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：HCT11M；CDx4HCT11 Triple 3-Input AND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

丝印代码：HCT11M；CDx4HCT11 Triple 3-Input AND Gates

1 Features • LSTTL input logic compatible – VIL(max) = 0.8 V, VIH(min) = 2 V • CMOS input logic compatible – II ≤ 1 μA at VOL, VOH • Buffered inputs • 4.5 V to 5.5 V operation • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power r

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：346.89 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：55.1 Kbytes Page：8 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：346.89 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：765.86 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：440.26 Kbytes Page：13 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：616 Kbytes Page：15 Pages

High Speed CMOS Logic Triple 3-Input AND Gate

文件：33.84 Kbytes Page：6 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

封装/外壳：14-DIP（0.300"，7.62mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC GATE AND 3CH 3-INP 14DIP 集成电路（IC） 门和反相器

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

High Speed CMOS Logic Triple 3-Input AND Gate

文件：33.84 Kbytes Page：6 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：616 Kbytes Page：15 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：440.26 Kbytes Page：13 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC GATE AND 3CH 3-INP 14SOIC 集成电路（IC） 门和反相器

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：616 Kbytes Page：15 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：440.26 Kbytes Page：13 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：616 Kbytes Page：15 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：616 Kbytes Page：15 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：616 Kbytes Page：15 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：440.26 Kbytes Page：13 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

Triple 3-input AND gate

GENERAL DESCRIPTION The 74HC/HCT11 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT11 provide the 3-input AND function. FEATURES • Output capability: standard • ICC categor

Triple 3-input AND gate

GENERAL DESCRIPTION The 74HC/HCT11 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT11 provide the 3-input AND function. FEATURES • Output capability: standard • ICC categor

Triple 3-input AND gate

GENERAL DESCRIPTION The 74HC/HCT11 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT11 provide the 3-input AND function. FEATURES • Output capability: standard • ICC categor

Triple 3-input AND gate

GENERAL DESCRIPTION The 74HC/HCT11 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT11 provide the 3-input AND function. FEATURES • Output capability: standard • ICC categor