CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

封装/外壳：16-DIP（0.300"，7.62mm） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 16DIP 集成电路（IC） 触发器

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：346.89 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：765.86 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

Dual JK flip-flop with set and reset; negative-edge trigger

1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate indepen

Dual JK flip-flop with set and reset; negative-edge trigger

1. General description The 74HC112; 74HCT112 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (nCP) set (nSD) and reset (nRD) inputs. It also has complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate indepen

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip

Dual JK flip-flop with set and reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Asynchronous set and reset • Output capability: standard • ICC category: flip