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CD74HC73MT价格
参考价格：￥2.6268
型号：CD74HC73MT 品牌：Texas 备注：这里有CD74HC73MT多少钱，2025年最近7天走势，今日出价，今日竞价，CD74HC73MT批发/采购报价，CD74HC73MT行情走势销售排行榜，CD74HC73MT报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CD74HC73MT | CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger 1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS | TI 德州仪器 |   | |
CD74HC73MT | 封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 14SOIC 集成电路（IC） 触发器 | TI 德州仪器 | | |
CD74HC73MT | Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：1.00769 Mbytes Page：18 Pages | TI 德州仪器 | | |
CD74HC73MT | Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：266.53 Kbytes Page：13 Pages | TI 德州仪器 | | |
CD74HC73MT | Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：452.31 Kbytes Page：15 Pages | TI 德州仪器 | | |
CD74HC73MT | Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：422.72 Kbytes Page：15 Pages | TI 德州仪器 | | |
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：422.72 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：266.53 Kbytes Page：13 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：422.72 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual JK flip-flop with reset; negative-edge trigger General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: | Philips 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger | ETC 知名厂家 | ETC | | |
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n | NEXPERIA 安世 | | ||
Dual JK flip-flop with reset; negative-edge trigger | ETC 知名厂家 | ETC | | |
Dual JK flip-flop with reset; negative-edge trigger General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: | Philips 飞利浦 | |
CD74HC73MT产品属性
- 类型
描述
- 型号
CD74HC73MT
- 功能描述
触发器 Hi-Spd CMOS Dual Neg J-K Flip-Flop
- RoHS
否
- 制造商
Texas Instruments
- 电路数量
2
- 逻辑系列
SN74
- 逻辑类型
D-Type Flip-Flop
- 极性
Inverting, Non-Inverting
- 输入类型
CMOS
- 传播延迟时间
4.4 ns
- 高电平输出电流
- 16 mA
- 低电平输出电流
16 mA
- 电源电压-最大
5.5 V
- 最大工作温度
+ 85 C
- 安装风格
SMD/SMT
- 封装/箱体
X2SON-8
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
24+ |
SMD |
10000 |
全新原厂原装，进口正品现货，正规渠道可含税！！ |
|||
TI |
20+ |
NA |
53650 |
TI原装主营-可开原型号增税票 |
|||
HARRIS |
24+/25+ |
239 |
原装正品现货库存价优 |
||||
TI |
22+ |
14SOIC |
9000 |
原厂渠道,现货配单 |
|||
25+ |
DIP |
2700 |
全新原装自家现货优势! |
||||
HAR |
2015+ |
SOP/DIP |
19889 |
一级代理原装现货,特价热卖! |
|||
25+23+ |
14 |
34569 |
绝对原装正品全新进口深圳现货 |
||||
24+ |
SOP |
220 |
|||||
TI |
24+ |
TSSOP16 |
6618 |
公司现货库存,支持实单 |
|||
TI/德州仪器 |
23+ |
14-SOIC |
4080 |
原装正品代理渠道价格优势 |
CD74HC73MT规格书下载地址
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深圳科雨电子有限公司，联系人：卢小姐 手机：18975515225 原装正品 大量现货，有需要的可以联系我 QQ:97877805 微信：wei555222777
2019-6-10
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