丝印代码：CD74HC73E；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Dual J-K Flip-Flop with Reset

Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative–edge clocked and has an active

Dual J-K Flip-Flop with Reset

Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative–edge clocked and has an active

Dual J-K Flip-Flop with Reset

Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative–edge clocked and has an active