High-Speed CMOS Logic Digital Phase-Locked Loop

Features • Digital Design Avoids Analog Compensation Errors • Easily Cascadable for Higher Order Loops • Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) • Dynamically V

High-Speed CMOS Logic Digital Phase-Locked-Loop

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High-Speed CMOS Logic Digital Phase-Locked Loop

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High-Speed CMOS Logic Digital Phase-Locked Loop

Features • Digital Design Avoids Analog Compensation Errors • Easily Cascadable for Higher Order Loops • Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) • Dynamically V

Digital phase-locked-loop filter

GENERAL DESCRIPTION The 74HC/HCT297 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT297 are designed to provide a simple, cost-effective solution to high-accuracy, digital,