High-Speed CMOS Logic Digital Phase-Locked Loop

Features • Digital Design Avoids Analog Compensation Errors • Easily Cascadable for Higher Order Loops • Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) • Dynamically V

高速 CMOS 逻辑数字锁相环

The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL).\n These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits • Digital Design Avoids Analog Compensation Errors\n• Useful Frequency Range \n• I/D-Clock DC to 35MHz (Typ)\n• Very Narrow Bandwidth Attainable\n• Output Capability \n• Bus Driver I/DOUT\n• Bus Driver Outputs 15 LSTTL Loads\n• Significant Power Reduction Compared to LSTTL Logic ICs\n• High No;

High-Speed CMOS Logic Digital Phase-Locked-Loop

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High-Speed CMOS Logic Digital Phase-Locked Loop

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丝印代码：CD74HC297E；High-Speed CMOS Logic Digital Phase-Locked Loop

Features • Digital Design Avoids Analog Compensation Errors • Easily Cascadable for Higher Order Loops • Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) • Dynamically V

丝印代码：CD74HC297E；High-Speed CMOS Logic Digital Phase-Locked Loop

Features • Digital Design Avoids Analog Compensation Errors • Easily Cascadable for Higher Order Loops • Useful Frequency Range - K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ) - I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ) • Dynamically V

High-Speed CMOS Logic Digital Phase-Locked Loop

文件：251.63 Kbytes Page：15 Pages

High-Speed CMOS Logic Digital Phase-Locked Loop

文件：255.96 Kbytes Page：15 Pages

封装/外壳：16-DIP（0.300"，7.62mm） 包装：管件 描述：IC DIGITAL PLL 16-DIP 集成电路（IC） 时钟发生器，PLL，频率合成器

High-Speed CMOS Logic Digital Phase-Locked Loop

文件：251.63 Kbytes Page：15 Pages

封装/外壳：16-DIP（0.300"，7.62mm） 包装：管件 描述：IC DIGITAL PHASE-LOCKD LOOP 16-D 集成电路（IC） 时钟发生器，PLL，频率合成器

Digital phase-locked-loop filter

GENERAL DESCRIPTION The 74HC/HCT297 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT297 are designed to provide a simple, cost-effective solution to high-accuracy, digital,