CDx4HC11 Triple 3-Input AND Gates

1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si

军用 3 通道、3 输入、2V 至 6V 与门

This device contains three independent 3-input AND gates. Each gate performs the Boolean function Y = A ● B ● C in positive logic. • Buffered inputs\n• Wide operating voltage range: 2 V to 6 V\n• Wide operating temperature range: –55°C to +125°C\n• Supports fanout up to 10 LSTTL loads\n• Significant power reduction compared to LSTTL logic ICs;

High-Speed CMOS Logic Triple 3-Input AND Gate

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High Speed CMOS Logic Triple 3-Input AND Gate

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High-Speed CMOS Logic Triple 3-Input AND Gate

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High-Speed CMOS Logic Triple 3-Input AND Gate

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丝印代码：CD54HC11F；CDx4HC11 Triple 3-Input AND Gates

1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si

丝印代码：CD54HC11F；CDx4HC11 Triple 3-Input AND Gates

1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si

具有设置与复位端的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器

The ’HC112 and ’HCT112 utilize silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.\n\n These flip-flops have independent J, K, Set, Reset, a • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times\n• Complementary Outputs\n• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C\n• Standard Outputs . . . . . 10 LSTTL Loads\n• Wide Operating Temperature Range . . . –55°C to 125°C\n• Significant Pow;

CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

丝印代码：8408801EA；CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous set and reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard output

丝印代码：8404801CA；CDx4HC11 Triple 3-Input AND Gates

1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si

丝印代码：8404801CA；CDx4HC11 Triple 3-Input AND Gates

1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Combining power good signals • Enable digital si

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：440.26 Kbytes Page：13 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：616 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：346.89 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：757.59 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：765.86 Kbytes Page：20 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：643.79 Kbytes Page：18 Pages

Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger

文件：346.89 Kbytes Page：13 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

High Speed CMOS Logic Triple 3-Input AND Gate

文件：33.84 Kbytes Page：6 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：616 Kbytes Page：15 Pages

High Speed CMOS Logic Triple 3-Input AND Gate

文件：33.84 Kbytes Page：6 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：260.86 Kbytes Page：11 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：616 Kbytes Page：15 Pages

High-Speed CMOS Logic Triple 3-Input AND Gate

文件：440.26 Kbytes Page：13 Pages

TRIPLE 3-INPUT AND GATE

Description The M54HCxxx and M54HCTxxx series are composed of over 90 types of high speed CMOS functions specifically designed to meet the radiation requirements of the aerospace industry. It includes a large set of gates, Flip-Flops, Multiplexers, Counters, Bus interface and several other functi

TRIPLE 3-INPUT POSITIVE-AND GATES

文件：518.94 Kbytes Page：15 Pages

TRIPLE 3-INPUT POSITIVE-AND GATES

文件：518.94 Kbytes Page：15 Pages