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CD54HC10价格
参考价格：￥30.2984
型号：CD54HC10F3A 品牌：Texas Instruments 备注：这里有CD54HC10多少钱，2025年最近7天走势，今日出价，今日竞价，CD54HC10批发/采购报价，CD54HC10行情走势销售排行榜，CD54HC10报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CD54HC10 | High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：265.51 Kbytes Page：10 Pages | TI 德州仪器 |   | |
CD54HC10 | High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：261.209 Kbytes Page：11 Pages | TI 德州仪器 | | |
CD54HC10 | High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：32.159 Kbytes Page：5 Pages | TI 德州仪器 | | |
CD54HC10 | High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：614.15 Kbytes Page：15 Pages | TI 德州仪器 | | |
CD54HC10 | 军用 3 通道、3 输入、2V 至 6V 与非门 | TI 德州仪器 | | |
Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi | TI 德州仪器 | | ||
CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 D | TI 德州仪器 | | ||
CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 D | TI 德州仪器 | | ||
CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 D | TI 德州仪器 | | ||
CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 D | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：32.159 Kbytes Page：5 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：261.209 Kbytes Page：11 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：614.15 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：266.26 Kbytes Page：11 Pages | TI 德州仪器 | | ||
具有复位功能的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器 | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：266.26 Kbytes Page：11 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：279.59 Kbytes Page：12 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：454.62 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：347.95 Kbytes Page：16 Pages | TI 德州仪器 | | ||
具有设置和复位端的高速 CMOS 逻辑双路正边沿触发式 J-K 触发器 | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：347.95 Kbytes Page：16 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：454.62 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：347.95 Kbytes Page：16 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：279.59 Kbytes Page：12 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：454.62 Kbytes Page：15 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：265.51 Kbytes Page：10 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：261.209 Kbytes Page：11 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：32.159 Kbytes Page：5 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：265.51 Kbytes Page：10 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：261.209 Kbytes Page：11 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：614.15 Kbytes Page：15 Pages | TI 德州仪器 | |
CD54HC10产品属性
- 类型
描述
- 型号
CD54HC10
- 制造商
Texas Instruments
- 功能描述
Flip Flop JK-Type Neg-Edge 2-Element 14-Pin CDIP Tube
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI |
25+ |
CDIP14 |
15 |
原装正品,假一罚十! |
|||
TI(德州仪器) |
23+ |
- |
15000 |
专业帮助客户找货 配单,诚信可靠! |
|||
Rochester |
25+ |
电联咨询 |
7800 |
公司现货,提供拆样技术支持 |
|||
HAR |
23+ |
CDIP16 |
10000 |
原厂授权一级代理,专业海外优势订货,价格优势、品种 |
|||
TI |
三年内 |
1983 |
只做原装正品 |
||||
TI |
24+ |
16L CDIP (J) |
8000 |
新到现货，只做全新原装正品 |
|||
TI |
25+ |
16L CD.. |
270 |
全新现货 |
|||
TI |
2511 |
14L CDIP (J) |
3200 |
电子元器件采购降本 30%!盈慧通原厂直采,砍掉中间差价 |
|||
HAR |
25+ |
QFP |
3200 |
全新原装、诚信经营、公司现货销售! |
|||
24+ |
N/A |
46000 |
一级代理-主营优势-实惠价格-不悔选择 |
CD54HC10规格书下载地址
CD54HC10参数引脚图相关
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- CD5369B
- CD5368B
- CD5367B
- CD5366B
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- CD5364B
- CD5363B
- CD5362B
- CD5361B
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DdatasheetPDF页码索引
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