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CD54HC10价格
参考价格：￥30.2984
型号：CD54HC10F3A 品牌：Texas Instruments 备注：这里有CD54HC10多少钱，2025年最近7天走势，今日出价，今日竞价，CD54HC10批发/采购报价，CD54HC10行情走势销售排行榜，CD54HC10报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CD54HC10 | CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 D | TI 德州仪器 |   | |
CD54HC10 | 军用 3 通道、3 输入、2V 至 6V 与非门 | TI 德州仪器 | | |
CD54HC10 | High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：265.51 Kbytes Page：10 Pages | TI 德州仪器 | | |
CD54HC10 | High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：261.209 Kbytes Page：11 Pages | TI 德州仪器 | | |
CD54HC10 | High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：32.159 Kbytes Page：5 Pages | TI 德州仪器 | | |
CD54HC10 | High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：614.15 Kbytes Page：15 Pages | TI 德州仪器 | | |
Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger Features • Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times • Asynchronous Reset • Complementary Outputs • Buffered Inputs • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger Features • Asynchronous Set and Reset • Schmitt Trigger Clock Inputs • Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wi | TI 德州仪器 | | ||
CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 D | TI 德州仪器 | | ||
CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 D | TI 德州仪器 | | ||
CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 D | TI 德州仪器 | | ||
CDx4HC10 Triple 3-Input NAND Gates 1 Features • Buffered inputs • Wide operating voltage range: 2 V to 6 V • Wide operating temperature range: -55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 D | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：32.159 Kbytes Page：5 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：261.209 Kbytes Page：11 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：614.15 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：266.26 Kbytes Page：11 Pages | TI 德州仪器 | | ||
具有复位功能的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器 | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：451.69 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：624.14 Kbytes Page：16 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Reset Negative-Edge Trigger 文件：266.26 Kbytes Page：11 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：279.59 Kbytes Page：12 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：454.62 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：347.95 Kbytes Page：16 Pages | TI 德州仪器 | | ||
具有设置和复位端的高速 CMOS 逻辑双路正边沿触发式 J-K 触发器 | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：347.95 Kbytes Page：16 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：454.62 Kbytes Page：15 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：347.95 Kbytes Page：16 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：279.59 Kbytes Page：12 Pages | TI 德州仪器 | | ||
Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger 文件：454.62 Kbytes Page：15 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：265.51 Kbytes Page：10 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：261.209 Kbytes Page：11 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：32.159 Kbytes Page：5 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：265.51 Kbytes Page：10 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：261.209 Kbytes Page：11 Pages | TI 德州仪器 | | ||
High-Speed CMOS Logic Triple 3-Input NAND Gate 文件：614.15 Kbytes Page：15 Pages | TI 德州仪器 | |
CD54HC10产品属性
- 类型
描述
- 型号
CD54HC10
- 制造商
Texas Instruments
- 功能描述
Flip Flop JK-Type Neg-Edge 2-Element 14-Pin CDIP Tube
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI/德州仪器 |
24+ |
NA/ |
3265 |
原装现货,当天可交货,原型号开票 |
|||
TI |
25+ |
CDIP14 |
15 |
原装正品,假一罚十! |
|||
HARRIS |
23+ |
NA |
131 |
专做原装正品,假一罚百! |
|||
TI |
20+ |
N/A |
3600 |
专业配单,原装正品假一罚十,代理渠道价格优 |
|||
TI/德州仪器 |
22+ |
DIP16 |
12245 |
现货,原厂原装假一罚十! |
|||
TI |
25+ |
14L CDIP (J) |
30000 |
代理全新原装现货,价格优势 |
|||
22+ |
5000 |
只做原装鄙视假货15118075546 |
|||||
HARRIS/哈里斯 |
25+ |
DIP14 |
880000 |
明嘉莱只做原装正品现货 |
|||
RCA |
25+23+ |
DIP14 |
21569 |
绝对原装正品全新进口深圳现货 |
|||
HARRIS |
25+ |
DIP14 |
18 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
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CD54HC10规格书下载地址
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