CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

CD4000系列 逻辑芯片

CMOS 双路 64 级静态移位寄存器

CMOS DUAL 64-STAGE STATIC SHIFT REGISTER

文件：245.55 Kbytes Page：6 Pages

Cmos Dual 64-stage Static Shift Register

文件：414.75 Kbytes Page：9 Pages

丝印代码：CD4517BE；CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

丝印代码：CD4517BE；CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

丝印代码：CD4517BF3A；CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

丝印代码：CD4517BF3A；CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

CMOS Dual 64-Stage Static Shift Register

Features: ® Low quiescent current — 10 nA/pkg (typ.) atVpp=5V ® Clock frequency 12 MHz (typ.} at Vpp=10V ® Schmitt trigger clock inputs allow operation with very slow clock rise and fall times = Capable of driving two low-power TTL loads, one low- power Schottky TTL load, or two HTL loads

CMOS Dual 64-Stage Static Shift Register

Description CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32rd, 48th, and 64th stages. These taps also serve as input points allowing data to be inputted

Cmos Dual 64-stage Static Shift Register

文件：414.75 Kbytes Page：9 Pages

3-state parallel outputs for connection to common bus

文件：1.11921 Mbytes Page：14 Pages

CMOS Dual 64-Stage Static Shift Register

文件：396.35 Kbytes Page：9 Pages

Cmos Dual 64-stage Static Shift Register

文件：414.75 Kbytes Page：9 Pages

封装/外壳：16-DIP（0.300"，7.62mm） 功能：串行至并行 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC SHIFT REG STATIC DUAL 16-DIP 集成电路（IC） 移位寄存器

Cmos Dual 64-stage Static Shift Register

文件：414.75 Kbytes Page：9 Pages

CMOS Dual 64-Stage Static Shift Register

文件：396.35 Kbytes Page：9 Pages

Cmos Dual 64-stage Static Shift Register

文件：414.75 Kbytes Page：9 Pages

CMOS Dual 64-Stage Static Shift Register

文件：396.35 Kbytes Page：9 Pages

Cmos Dual 64-stage Static Shift Register

文件：414.75 Kbytes Page：9 Pages

CMOS 双路 64 级静态移位寄存器

DUAL 64-STAGE STATIC SHIFT REGISTER

DESCRIPTION The HCC4517B (extended temperature range) and HCF4517B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package. ■ CLOCK FREQUENCY 12MHz (TYP.) AT VDD = 10V ■ SCHMITT TRIGGER CLOCK INPUTS ALLOW OPERATION WITH V

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

Dual 64-bit static shift register

DESCRIPTION The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (CP), data input (D), parallel input-enable/output-enable (PE/EO) and four 3-state outputs of the 16th, 32nd, 48th and 64th bit positions (O16 to O64). Data at the D inp

Dual 64-bit Static Shift Register

Dual 64−Bit Static Shift Register

Dual 64-Bit Static Shift Register