CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

CMOS 4 位锁存器/4 至 16 线解码器

CD4514B and CD4515B consist of a 4-bit strobed latch and a 4-to-16-line decoder. The latches hold the last inputdata presented prior to the strobe transition from 1 to 0. Inhibit control allows all outputs to be placed at 0 (CD4514B)or 1 (CD4515B) regardless of the state of the data or strobe inputs CD4514B Output \"High\" on Select CD4515B Output \"Low\" on Select \n• Inhibit control\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• 1 V at VDD = 5 V\n• 2.5 V at VDD = 15 V\n• 5-V, 10-V, and 15-V parametric ratings\n• Meets all requirement;

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

Cmos 4-Bit Latch/4-to-16 Line Decoders

文件：1.026599 Mbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：222.79 Kbytes Page：12 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

丝印代码：CD4515BM；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

丝印代码：CD4515BM；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

丝印代码：CD4515BM；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily used in decoding applications where low power dissipation

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are prima rily used in decoding applications where low power dissipa tion

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are prima rily used in decoding applications where low power dissipa tion

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily used in decoding applications where low power dissipation

丝印代码：7703201JA；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

丝印代码：7703201JA；CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

CMOS 4 位锁存器/4 至 16 线解码器

CD4514B and CD4515B consist of a 4-bit strobed latch and a 4-to-16-line decoder. The latches hold the last inputdata presented prior to the strobe transition from 1 to 0. Inhibit control allows all outputs to be placed at 0 (CD4514B)or 1 (CD4515B) regardless of the state of the data or strobe inputs CD4514B Output \"High\" on Select CD4515B Output \"Low\" on Select \n• Inhibit control\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• 1 V at VDD = 5 V\n• 2.5 V at VDD = 15 V\n• 5-V, 10-V, and 15-V parametric ratings\n• Meets all requirement;

CMOS 4-Bit Latch/4-to-16 Line Decoders

Description CD4514BMS and CD4515BMS consist of a 4-bit strobed latch and a 4-to-16-line decoder. The latches hold the last input data presented prior to the strobe transition from 1 to 0. Inhibit control allows all outputs to be placed at 0(CD4514BMS) or 1(CD4515BMS) regardless of the state of

4-Bit Latched/4-to-16 Line Decoders

文件：235.94 Kbytes Page：8 Pages

4-Bit Latched/4-to-16 Line Decoders

文件：135.98 Kbytes Page：6 Pages

4-Bit Latched/4-to-16 Line Decoders

文件：235.94 Kbytes Page：8 Pages

4-Bit Latched/4-to-16 Line Decoders

文件：235.94 Kbytes Page：8 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：222.79 Kbytes Page：12 Pages

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

封装/外壳：24-DIP（0.600"，15.24mm） 包装：管件 描述：IC DECODER/DEMUX 1X4:16 24DIP 集成电路（IC） 信号开关，多路复用器，解码器

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

封装/外壳：24-DIP（0.600"，15.24mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1X4:16 24DIP 集成电路（IC） 信号开关，多路复用器，解码器

Cmos 4-Bit Latch/4-to-16 Line Decoders

文件：1.026599 Mbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：222.79 Kbytes Page：12 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：222.79 Kbytes Page：12 Pages

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

Cmos 4-Bit Latch/4-to-16 Line Decoders

文件：1.026599 Mbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

4-Bit Latched/4-to-16 Line Decoders

文件：135.98 Kbytes Page：6 Pages

Cmos 4-Bit Latch/4-to-16 Line Decoders

文件：1.026599 Mbytes Page：15 Pages

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：222.79 Kbytes Page：12 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

Cmos 4-Bit Latch/4-to-16 Line Decoders

文件：1.026599 Mbytes Page：15 Pages

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

Cmos 4-Bit Latch/4-to-16 Line Decoders

文件：1.026599 Mbytes Page：15 Pages

CMOS 4-Bit Latch/4-to-16 Line Decoders

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor in a plastic full-pack envelope intended for use in horizontal deflection circuits of colour television receivers an p.c monitors. Features exceptional tolerance to base drive and collect

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor with an integrated damper diode in a plastic full-pack envelope intended for use in horizontal deflection circuits of colour television receivers an p.c monitors. Features exceptional toler

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor with an integrated damper diode in a plastic full-pack envelope intended for use in horizontal deflection circuits of colour television receivers an p.c monitors. Features exceptional toler

1-of-16 decoder/demultiplexer with input latches

DESCRIPTION The HEF4515B is a 1-of-16 decoder/demultiplexer, having four binary weighted address inputs (A0 to A3), a latch enable input (EL), and an active LOW enable input (E). The 16 outputs (O0 to O15) are mutually exclusive active LOW. When EL is HIGH, the selected output is determined by th

1-of-16 decoder/demultiplexer with input latches

DESCRIPTION The HEF4515B is a 1-of-16 decoder/demultiplexer, having four binary weighted address inputs (A0 to A3), a latch enable input (EL), and an active LOW enable input (E). The 16 outputs (O0 to O15) are mutually exclusive active LOW. When EL is HIGH, the selected output is determined by th

1-of-16 decoder/demultiplexer with input latches

1-of-16 decoder/demultiplexer with input latches

1-of-16 decoder/demultiplexer with input latches

4-Bit Transparent Latch/4-to-16 Line Decoder

4−Bit Transparent Latch / 4−to−16 Line Decoder

4-Bit Transparent Latch/4-to-16 Line Decoder

CMOS 4-TO-16 LINE DECODERS WITH LATCH