CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

封装/外壳：24-DIP（0.600"，15.24mm） 包装：管件 描述：IC DECODER/DEMUX 1X4:16 24DIP 集成电路（IC） 信号开关，多路复用器，解码器

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：222.79 Kbytes Page：12 Pages

CMOS 4-Bit Latch 4-to-16 Line Decoders

文件：978.31 Kbytes Page：15 Pages

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

文件：995.38 Kbytes Page：15 Pages

封装/外壳：24-DIP（0.600"，15.24mm） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1X4:16 24DIP 集成电路（IC） 信号开关，多路复用器，解码器

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor in a plastic full-pack envelope intended for use in horizontal deflection circuits of colour television receivers an p.c monitors. Features exceptional tolerance to base drive and collect

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor with an integrated damper diode in a plastic full-pack envelope intended for use in horizontal deflection circuits of colour television receivers an p.c monitors. Features exceptional toler

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor with an integrated damper diode in a plastic full-pack envelope intended for use in horizontal deflection circuits of colour television receivers an p.c monitors. Features exceptional toler

1-of-16 decoder/demultiplexer with input latches

DESCRIPTION The HEF4515B is a 1-of-16 decoder/demultiplexer, having four binary weighted address inputs (A0 to A3), a latch enable input (EL), and an active LOW enable input (E). The 16 outputs (O0 to O15) are mutually exclusive active LOW. When EL is HIGH, the selected output is determined by th

1-of-16 decoder/demultiplexer with input latches

DESCRIPTION The HEF4515B is a 1-of-16 decoder/demultiplexer, having four binary weighted address inputs (A0 to A3), a latch enable input (EL), and an active LOW enable input (E). The 16 outputs (O0 to O15) are mutually exclusive active LOW. When EL is HIGH, the selected output is determined by th

4-Bit Latched/4-to-16 Line Decoders

4-Bit Latched/4-to-16 Line Decoders

CMOS 4-BIT LATCH/4-TO-16 LINE DECODERS

4-Bit Latched/4-to-16 Line Decoders

1-of-16 decoder/demultiplexer with input latches

1-of-16 decoder/demultiplexer with input latches

1-of-16 decoder/demultiplexer with input latches

4-Bit Transparent Latch/4-to-16 Line Decoder

4−Bit Transparent Latch / 4−to−16 Line Decoder

4-Bit Transparent Latch/4-to-16 Line Decoder

CMOS 4-TO-16 LINE DECODERS WITH LATCH