CMOS Presettable Up/Down Counters

Features: Medium-speed operation fcr =8MHztyp.at10V Synchronous internal carry propagation Reset and Preset capability 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings & Standardized symmetrical output characteristics Maximum input current of 1 uA

CMOS Presettable Up/Down Counters

Features: Medium-speed operation fcr =8MHztyp.at10V Synchronous internal carry propagation Reset and Preset capability 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings & Standardized symmetrical output characteristics Maximum input current of 1 uA

CMOS Presettable Up/Down Counters

CD4510BMS Presettable BCD Up/Down Counter and the CD4516BMS Presettable Binary Up/Down counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as counters. These counters can be cleared by a high level on the RESET

CMOS Presettable Up/Down Counters

Features: Medium-speed operation fcr =8MHztyp.at10V Synchronous internal carry propagation Reset and Preset capability 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings & Standardized symmetrical output characteristics Maximum input current of 1 uA

CMOS Presettable Up/Down Counters

Features: Medium-speed operation fcr =8MHztyp.at10V Synchronous internal carry propagation Reset and Preset capability 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings & Standardized symmetrical output characteristics Maximum input current of 1 uA

CMOS Presettable Up/Down Counters

Features: Medium-speed operation fcr =8MHztyp.at10V Synchronous internal carry propagation Reset and Preset capability 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings & Standardized symmetrical output characteristics Maximum input current of 1 uA

CMOS Presettable Up/Down Counters

Features: Medium-speed operation fcr =8MHztyp.at10V Synchronous internal carry propagation Reset and Preset capability 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings & Standardized symmetrical output characteristics Maximum input current of 1 uA

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

BCD-to-7 Segment Latch/Decoder/Driver

General Description The CD4511BC BCD-to-seven segment latch/decoder/driver is constructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functions of a 4-bit storage latch, an 8421 BCD-to-seven seg

BCD-to-7 Segment Latch/Decoder/Driver

General Description The CD4511BC BCD-to-seven segment latch/decoder/driver is constructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functions of a 4-bit storage latch, an 8421 BCD-to-seven seg

BCD-to-7 Segment Latch/Decoder/Driver

General Description The CD4511BC BCD-to-seven segment latch/decoder/driver is constructed with complementary MOS (CMOS) enhancement mode devices and NPN bipolar output drivers in a single monolithic structure. The circuit provides the functions of a 4-bit storage latch, an 8421 BCD-to-seven seg

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Description CD4511BMS is a BCD-to-7-Segment latch decoder drivers constructed with CMOS logic and n-p-n bipolar transistor output devices on a single monolithic structure. These devices combine the low quiescent power dissipation and high noise immunity features of Intersil CMOS with n-p-n bipo

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS BCD-to-7-Segment Latch Decoder Drivers

Features: High-output-sourcing capability ........up to 25 mA |nput latches for BCD Code storage Lamp Test and Blanking capability = 7-segment outputs blanked for BCD input codes > 1001 100% tested for quiescent current at 20 V Max. input current of 1 uA at 18 V, overa full package

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

8-Channel Buffered Data Selector

General Description The CD4512BC buffered 8-channel data selector is a complementary MOS (CMOS) circuit constructed with N- and P-channel enhancement mode transistors. This data selector is primarily used as a digital signal multiplexer selecting 1 of 8 inputs and routing the signal to a 3-STAT

8-Channel Buffered Data Selector

General Description The CD4512BC buffered 8-channel data selector is a complementary MOS (CMOS) circuit constructed with N- and P-channel enhancement mode transistors. This data selector is primarily used as a digital signal multiplexer selecting 1 of 8 inputs and routing the signal to a 3-STAT

8-Channel Buffered Data Selector

General Description The CD4512BC buffered 8-channel data selector is a complementary MOS (CMOS) circuit constructed with N- and P-channel enhancement mode transistors. This data selector is primarily used as a digital signal multiplexer selecting 1 of 8 inputs and routing the signal to a 3-STAT

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS Dual 4-Bit Latch

Features • High-Voltage Types (20-Volt Rating) • 3-State Outputs • Standardized, Symmetrical Output Characteristics • 100 Tested for Quiescent Current at 20V • 5V, 10V, and 15V Parametric Ratings • Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and 25oC

CMOS Dual 4-Bit Latch

Description CD4512BMS is an 8-channel data selector featuring a threestate output that can interface directly with, and drive, data lines of bus-oriented systems.     Features • High-Voltage Types (20-Volt Rating) • 3-State Outputs • Standardized, Symmetrical Output Characteristics • 100 Te

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 8-Channel Data Selector

Features: 3-state output Standardized, symmetrical output characteristiés = 100% tested for quiescent current at 20 V 5V, 10-V, and 15-V parametric ratings : Maximum input current of 1 uA at 18 V over full package- temperature range; 100 nA at 18 V and 25°C = Noise margin (over full

CMOS 4-Bit Latch/4-to-16 Line Decoders

Description CD4514BMS and CD4515BMS consist of a 4-bit strobed latch and a 4-to-16-line decoder. The latches hold the last input data presented prior to the strobe transition from 1 to 0. Inhibit control allows all outputs to be placed at 0(CD4514BMS) or 1(CD4515BMS) regardless of the state of

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are prima rily used in decoding applications where low power dissipa tion

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily used in decoding applications where low power dissipation

CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are prima rily used in decoding applications where low power dissipa tion

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are prima rily used in decoding applications where low power dissipa tion

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily used in decoding applications where low power dissipation

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily used in decoding applications where low power dissipation

4-Bit Latched/4-to-16 Line Decoders

General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are prima rily used in decoding applications where low power dissipa tion

CMOS 4-Bit Latch/4-to-16 Line Decoders

Features: ® Strobed input latch ® Inhibit contral u 100% tested for quiescent current at 20 V ® Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C u Noise margin (over full package temper- ature range): 1VatVpp= 5V 2VatVpp=10V 25VatVpp

BCD Up/Down Counter

BCD up/down counter

BCD up/down counter

CMOS BCD UP/DOWN COUNTER