CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

三态输出的8级移位存储总线寄存器

8位移位寄存器/3 态输出缓冲器

八位移位寄存器

CMOS 8-STAGE SHIFT-AND-STORE BUS REGISTER

文件：281.11 Kbytes Page：5 Pages

CMOS 8-STAGE SHIFT-AND-STORE BUS REGISTER

文件：1.11921 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

CMOS 8-STAGE SHIFT-AND-STORE BUS REGISTER

文件：1.11921 Mbytes Page：14 Pages

8-Bit Shift Register/Latch with 3-STATE Outputs

General Description The CD4094BC consists of an 8-bit shift register and a 3-STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (QS) can be used to cascade several devices. Data on the QSoutput is transfer

8-Bit Shift Register/Latch with 3-STATE Outputs

General Description The CD4094BC consists of an 8-bit shift register and a 3-STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (QS) can be used to cascade several devices. Data on the QSoutput is transfer

8-Bit Shift Register/Latch with 3-STATE Outputs

General Description The CD4094BC consists of an 8-bit shift register and a 3-STATE 8-bit latch. Data is shifted serially through the shift register on the positive transition of the clock. The output of the last stage (QS) can be used to cascade several devices. Data on the QSoutput is transfer

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Description CD4094BMS is a 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive clock trans

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

SEMICONDUCTORS

文件：2.43533 Mbytes Page：31 Pages

封装/外壳：16-DIP（0.300"，7.62mm） 功能：串行至并行 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC BUS REGISTER 8STAGE 16-DIP 集成电路（IC） 移位寄存器

CMOS 8-STAGE SHIFT-AND-STORE BUS REGISTER

文件：281.11 Kbytes Page：5 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-STAGE SHIFT-AND-STORE BUS REGISTER

文件：281.11 Kbytes Page：5 Pages

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

CMOS 8-STAGE SHIFT-AND-STORE BUS REGISTER

文件：1.11921 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

3-state parallel outputs for connection to common bus

文件：1.11921 Mbytes Page：14 Pages

封装/外壳：16-SOIC（0.209"，5.30mm 宽） 功能：串行至并行 包装：管件 描述：IC SHIFT/STORE BUS REGSTR 16SO 集成电路（IC） 移位寄存器

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Nus Register

文件：1.11953 Mbytes Page：14 Pages

CMOS 8-Stage Shift-and-Store Bus Register

文件：1.11992 Mbytes Page：14 Pages

8-bit compatible shift / store register

●Description BU4015B series ICs are 4-stage static shift registers, each consisting of 2 circuits. The D flip-flops of each stage share a common reset input, enabling asynchronous reset at any time. BU4021B series ICs are 8-bit static shift registers configured with 8 register cells, each o

KK Mini -2.50mm & 2.54mm Modular Interconnection System

文件：69.47 Kbytes Page：2 Pages

T1/E1/CEPT/ISDN-Pri Filter Module

文件：368.74 Kbytes Page：1 Pages

High Voltage CMOS Logic ICs >Logic>

文件：504.91 Kbytes Page：18 Pages