丝印代码：CM094B；CMOS 8-Stage Shift-and-Store Bus Register

Features: 3-state parallel outputs for connection to common bus Separate serial outputs synchronous to both positive and negative clock edges for cascading Medium speed operation — 5 MHz at 10 V (typ.) Standardized, symmetrical output characteristics 100% tested for quiescent curren

8-stage shift-and-store bus register

DESCRIPTION The HEF4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs O0 to O7. The parallel outputs may be connected directly to common bus lines.

8-stage shift-and-store bus register

DESCRIPTION The HEF4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs O0 to O7. The parallel outputs may be connected directly to common bus lines.

8-stage shift-and-store bus register

DESCRIPTION The HEF4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs O0 to O7. The parallel outputs may be connected directly to common bus lines.

J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER

J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER Dual operational amplifier µPC4094 is a high-speed version of the µPC4092. NECs unique high-speed PNP transistor (fT = 300 MHz) in the output stage realizes a high slew rate of 25 V/µs under voltage-follower conditions without an oscillation probl

J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER

J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER Dual operational amplifier µPC4094 is a high-speed version of the µPC4092. NECs unique high-speed PNP transistor (fT = 300 MHz) in the output stage realizes a high slew rate of 25 V/µs under voltage-follower conditions without an oscillation probl