封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 功能：并行或串行至串行 包装：管件 描述：IC SHIFT REG PIN/P-OUT 16-TSSOP 集成电路（IC） 移位寄存器

丝印代码：CM035B；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

丝印代码：CM035B；CMOS 4-Stage Parallel In/Parallel Out Shift Register

Features: ® 4-Stage clocked shift operation # Synchronous parallel entry on all 4 stages a JK inputs on first stage ® Asynchronous True/Complement control on all outputs ® Static flip-flop operation; Master-slave configuration ® Buffered inputs and outputs ® High speed — 12

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 功能：并行或串行至串行 包装：管件 描述：IC SHIFT REG PIN/P-OUT 16-TSSOP 集成电路（IC） 移位寄存器

CMOS 4-stage Paraller in/Paraller Out shift Register

文件：906.35 Kbytes Page：16 Pages

Parallel In/Parallel Out Shift Refister

文件：893.49 Kbytes Page：17 Pages

Parallel In/Parallel Out Shift Refister

文件：893.49 Kbytes Page：17 Pages

Parallel In/Parallel Out Shift Refister

文件：893.49 Kbytes Page：17 Pages

4-bit universal shift register

DESCRIPTION The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

4-bit universal shift register

DESCRIPTION The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

4-bit universal shift register

DESCRIPTION The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

4-bit universal shift register

DESCRIPTION The HEF4035B is a fully synchronous edge-triggered 4-bit shift register with a clock input (CP), four synchronous parallel data inputs (P0 to P3), two synchronous serial data inputs (J, K), a synchronous parallel enable input (PE), buffered parallel outputs from all 4-bit positions

POWER TRANSISTORS(16A,60-100V,150W)

MEDIUM-POWER COMPLEMENTARY SILICON TRANSISTORS ...designed for use as output devices in complementary general purpose amplifier applications. FEATURES: * High Gain Darlington Performance * DCCurrent Gain hFE = 3500(Typ) @ lc = 10A * Monolithic Construction with Built-in Base-Emitter Shunt Res