CMOSDualJ-KMaster-SlaveFlip-Flop

Description CD4027BMSisasinglemonolithicchipintegratedcircuitcontainingtwoidenticalcomplementary-symmetryJ-Kmasterslaveflip-flops.Eachflip-flophasprovisionsforindividualJ,K,SetReset,andClockinputsignals.BufferedQandQsignalsareprovidedasoutputs.Thisinput-out

CMOSDualJ-KMaster-SlaveFlip-Flop

Features •HighVoltageType(20VRating) •Set-ResetCapability •StaticFlip-FlopOperation-RetainsStateIndefinitely withClockLevelEither“High”or“Low” •MediumSpeedOperation-16MHz(typ.)ClockToggle Rateat10V •StandardizedSymmetricalOutputCharacteristics •100Test

DualJKflip-flop

DESCRIPTION TheHEF4027BisadualJKflip-flopwhichisedge-triggeredandfeaturesindependentsetdirect (SD),cleardirect(CD),clock(CP)inputsandoutputs(O,O).DataisacceptedwhenCPisLOW,andtransferredtotheoutputonthepositive-goingedgeoftheclock.TheactiveHIGHas

DUAL-J-KMASTER-SLAVEFLIP-FLOP

DESCRIPTION TheHCC4027B(extendedtemperaturerange)andHCF4027B(intermediatetemperaturerange)aremonolithicintegratedcircuit,availablein16-leaddualin-lineplasticorceramicpackageandplasticmicropackage. ■SET-RESETCAPABILITY ■STATICFLIP-FLOPOPERATION-RETAINS

StandardSizePushbuttons

GeneralSpecifications ElectricalCapacity(ResistiveLoad) PowerLevel(silver):3A@125VACor3A@250VACor3A@30VDC LogicLevel(gold):0.4VAmaximum@28VAC/DCmaximum (ApplicableRange0.1mA~0.1A@20mV~28V) Note:FindadditionalexplanationofoperatingrangeinSupplements

CMOSDUALJ-KMASTER-SLAVERFLIP-FLOP

文件：531 Kbytes Page：12 Pages

ThisapplicationnotedescribestheEVL6699-150W-SRdemonstration

文件：2.8896 Mbytes Page：41 Pages