CMOS Quad 2 Line to 1 Line Data Selector/Multiplexer

Description CD40257BMS is a data selector/multiplexer featuring three state outputs which can interface directly with and drive data lines of bus oriented systems. The CD40257BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4T Frit Seal DIP H1E Ceramic Flatpa

Buffered Triple 3-Input NAND Gate

General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered

3路3输入与非门

The CD4025 is a triple 3-input NOR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance.It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or • Wide supply voltage range from 3V to 15V\n• Fully static operation\n• 5V, 10V, and 15V parametric ratings\n• Standardized symmetrical output characteristics\n• Inputs and outputs are protected against electrostatic effects\n• Specified from -40℃ to +125℃\n• Packaging information: DIP14/SOP14/TSSOP;

Buffered Triple 3-Input NAND,NOR Gate

文件：127.67 Kbytes Page：6 Pages

CMOS QUAD 2-LINE-TO-1-LINE DATA SELECTOR/MULTIPLEXER

文件：182.09 Kbytes Page：4 Pages

SEMICONDUCTORS

文件：2.43533 Mbytes Page：31 Pages

丝印代码：CD40257BE；CMOS Quad 2-Line-to-1-Line Data Selector/Multi plexer

Features: | ® 3-state outputs | ® Standardized, symmetrical output characteristics 8 100% tested for quigscent current at 0V . | 8 Maximum input current of uA at 18V ~~ | over full package-temperature range; | 100 nA at 18 V.and 25°C | Noise margin (aver full package- | temperature

丝印代码：CD40257BE；CMOS Quad 2-Line-to-1-Line Data Selector/Multi plexer

Features: | ® 3-state outputs | ® Standardized, symmetrical output characteristics 8 100% tested for quigscent current at 0V . | 8 Maximum input current of uA at 18V ~~ | over full package-temperature range; | 100 nA at 18 V.and 25°C | Noise margin (aver full package- | temperature

丝印代码：CD40257BE；CMOS Quad 2-Line-to-1-Line Data Selector/Multi plexer

Features: | ® 3-state outputs | ® Standardized, symmetrical output characteristics 8 100% tested for quigscent current at 0V . | 8 Maximum input current of uA at 18V ~~ | over full package-temperature range; | 100 nA at 18 V.and 25°C | Noise margin (aver full package- | temperature

丝印代码：CD40257BF3A；CMOS Quad 2-Line-to-1-Line Data Selector/Multi plexer

Features: | ® 3-state outputs | ® Standardized, symmetrical output characteristics 8 100% tested for quigscent current at 0V . | 8 Maximum input current of uA at 18V ~~ | over full package-temperature range; | 100 nA at 18 V.and 25°C | Noise margin (aver full package- | temperature

丝印代码：CD40257BF3A；CMOS Quad 2-Line-to-1-Line Data Selector/Multi plexer

Features: | ® 3-state outputs | ® Standardized, symmetrical output characteristics 8 100% tested for quigscent current at 0V . | 8 Maximum input current of uA at 18V ~~ | over full package-temperature range; | 100 nA at 18 V.and 25°C | Noise margin (aver full package- | temperature

丝印代码：CD40257BM；CMOS Quad 2-Line-to-1-Line Data Selector/Multi plexer

Features: | ® 3-state outputs | ® Standardized, symmetrical output characteristics 8 100% tested for quigscent current at 0V . | 8 Maximum input current of uA at 18V ~~ | over full package-temperature range; | 100 nA at 18 V.and 25°C | Noise margin (aver full package- | temperature

丝印代码：CD40257BM；CMOS Quad 2-Line-to-1-Line Data Selector/Multi plexer

Features: | ® 3-state outputs | ® Standardized, symmetrical output characteristics 8 100% tested for quigscent current at 0V . | 8 Maximum input current of uA at 18V ~~ | over full package-temperature range; | 100 nA at 18 V.and 25°C | Noise margin (aver full package- | temperature

丝印代码：CD4025BE；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025BE；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025BE；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025BF；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025BF；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025BF3A；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025BF3A；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025BM；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025BM；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025BM；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025BM；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025B；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CD4025B；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

CMOS Quad 2-Line-to-1-Line Data Selector/Multi plexer

Features: | ® 3-state outputs | ® Standardized, symmetrical output characteristics 8 100% tested for quigscent current at 0V . | 8 Maximum input current of uA at 18V ~~ | over full package-temperature range; | 100 nA at 18 V.and 25°C | Noise margin (aver full package- | temperature

CMOS 四路 2 线至 1 线数据选择器/多路复用器

CD40257B is a Data Selector/Multiplexer featuring three-state outputs which can interface directly with and drive data lines of bus-oriented systems.\n\n The CD40257B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), • 3-state outputs\n• Standardized, symmetrical output characteristics\n• 100% tested for quiescent current at 20 V\n• Maximum Input current of 1 µA at 18 V over full package temperature range: 100 nA at 18 V and 25°C\n• Noise Margin (over full package-temperature range):      1 V at VDD = 5 V   ;

CMOS Quad 2-Line-to-1-Line Data Selector/Multi plexer

Features: | ® 3-state outputs | ® Standardized, symmetrical output characteristics 8 100% tested for quigscent current at 0V . | 8 Maximum input current of uA at 18V ~~ | over full package-temperature range; | 100 nA at 18 V.and 25°C | Noise margin (aver full package- | temperature

CMOS Quad 2 Line to 1 Line Data Selector/Multiplexer

Description\nCD40257BMS is a data selector/multiplexer featuring three state outputs which can interface directly with and drive data lines of bus oriented systems. The CD40257BMS is supplied in these 16-lead outline\npackages:\nBraze Seal DIP H4T\nFrit Seal DIP H1E\nCeramic Flatpack H3X

CMOS Quad 2 Line to 1 Line Data Selector/Multiplexer

Description CD40257BMS is a data selector/multiplexer featuring three state outputs which can interface directly with and drive data lines of bus oriented systems. The CD40257BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4T Frit Seal DIP H1E Ceramic Flatpa

CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

CMOS NOR Gate

Description CD4000BMS - Dual 3 Plus Inverter CD4001BMS - Quad 2 Input CD4002BMS - Dual 4 Input CD4025BMS - Triple 3 Input CD4000BMS, CD4001BMS, CD4002BMS, and CD4025BMS NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing f

CMOS NOR Gate

Features • High-Voltage Types (20V Rating) • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V • Buffered Inputs and Outputs • Standard Symmetrical Output Characteristics • 100 Tested for Maximum Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Curre

丝印代码：CM025B；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CM025B；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

丝印代码：CM025B；CMOS NOR Gates

Features: = Propagation delay tima = 60 ns (typ.) at CL =50pF, Vpp=10V = Buffered inputs and outputs = Standardized symmetrical output characteristics = 100% tested for maximum quiescent current at 20 V ® 5-V, 10.V, and 15-V parametric ratings = Maximum input current of 1 uA at 18 V ov

CMOS QUAD 2-LINE-TO-1-LINE DATA SELECTOR/MULTIPLEXER

文件：182.09 Kbytes Page：4 Pages

CMOS Quad 2-Line-to-1-Line Data Selector /Multiflexer

文件：448.62 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Date Selector/Multi plexer

文件：421.15 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Data Selector /Multiflexer

文件：448.62 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Data Selector /Multiflexer

文件：448.62 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Date Selector/Multi plexer

文件：421.15 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Data Selector /Multiflexer

文件：448.62 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Date Selector/Multi plexer

文件：421.15 Kbytes Page：10 Pages

封装/外壳：16-DIP（0.300"，7.62mm） 包装：卷带（TR） 描述：IC MULTIPLEXER 4 X 1:2 16DIP 集成电路（IC） 信号开关，多路复用器，解码器

CMOS Quad 2-Line-to-1-Line Date Selector/Multi plexer

文件：421.15 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Data Selector /Multiflexer

文件：448.62 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Date Selector/Multi plexer

文件：421.15 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Data Selector /Multiflexer

文件：448.62 Kbytes Page：10 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC MULTIPLEXER 4 X 1:2 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

CMOS Quad 2-Line-to-1-Line Date Selector/Multi plexer

文件：421.15 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Data Selector /Multiflexer

文件：448.62 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Date Selector/Multi plexer

文件：421.15 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Data Selector /Multiflexer

文件：448.62 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Date Selector/Multi plexer

文件：421.15 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Date Selector/Multi plexer

文件：421.15 Kbytes Page：10 Pages

CMOS Quad 2-Line-to-1-Line Date Selector/Multi plexer

文件：421.15 Kbytes Page：10 Pages

CMOS NOR Gates

文件：1.18416 Mbytes Page：18 Pages

NOR GATE

Triple 3-input NOR Gate

Triple 3-input NOR gate

Triple 3-input NOR gate

B-Suffix Series CMOS Gates

B-SUFFIX SERIES CMOS GATES

B-Suffix Series CMOS Gates

B−Suffix Series CMOS Gates

B-Suffix Series CMOS Gates

B-Suffix Series CMOS Gates

B-SUFFIX SERIES CMOS GATES

COMPLEMENTARY METAL OXIDE SILICON

INPUT NOR GATE