Decade Counter with Asynchronous Clear

文件：150.85 Kbytes Page：8 Pages

CMOS Synchronous Programmable 4-Bit Counters

CMOS Synchronous Programmable 4-Bit Counters CD40160BMS, CD40161BMS, CD40162BMS and CD40163BMS are 4-bit synchronous programmable counters. The CLEAR function of the CD40162BMS and CD40163BMS is synchronous and a low level at the CLEAR input sets all four outputs low on the next positive CLOCK

CMOS Synchronous Programmable 4-Bit Counters

CMOS Synchronous Programmable 4-Bit CountersCD40160BMS, CD40161BMS, CD40162BMS and CD40163BMS are 4-bit synchronous programmable counters. The CLEAR function of the CD40162BMS and CD40163BMS is synchronous and a low level at the CLEAR input sets all four outputs low on the next positive CLOCK edge. • High-Voltage Types (20V Rating)\n• CD40160BMS Decade with Asynchronous Clear\n• CD40161BMS Binary with Asynchronous Clear\n• CD40162BMS Decade with Synchronous Clear\n• CD40163BMS Binary with Synchronous Clear\n• Internal Look-Ahead for Fast Counting\n• Carry Output for Cascading\n• Synchronously ;

Decade Counter with Asynchronous Clear

文件：150.85 Kbytes Page：8 Pages

Decade Counter with Asynchronous Clear

文件：150.85 Kbytes Page：8 Pages

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

4-bit synchronous decade counter with asynchronous reset

DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs (P0to P3), three synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP) and count ena

SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTERS

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Decade Counter with Asynchronous Clear

Decade Counter with Asynchronous Clear

SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTERS

SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTERS

4-bit synchronous decade counter with asynchronous reset

4-bit synchronous decade counter with asynchronous reset

4-bit synchronous decade counter with asynchronous reset

C2MOS DIGITAL INTERGRATED CIRCUIT SILICON MONOLITHIC