丝印代码：CD4015BM；CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

丝印代码：CD4015BM；CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

丝印代码：CD4015BM；CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

丝印代码：CD4015BM；CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

丝印代码：CD4015BM；CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

丝印代码：CD4015BM；CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

丝印代码：CD4015BM；CMOS Dual 4-Stage Static Shift Register

Features: ® Medium speed operation . 12 MHz (typ.) clock rate at Vpp — Vgg = 10 V ® Fully static operation ® 8 master-slave flip-flops plus input and output buffering ® 100% tested for quiescent current at 20 V ®5.V, 10-V, and 15-V parametric ratings ® Standardized, symmetr

CMOS Dual 4-stage Static Shift Register

文件：884.25 Kbytes Page：15 Pages

CMOS Dual 4-Stage Static Shift Register

文件：521.58 Kbytes Page：11 Pages

Dual 4-Bit Static Shift Register

文件：134.32 Kbytes Page：6 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：串行至并行 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DUAL 4STAGE SHIFT REG 16-SOIC 集成电路（IC） 移位寄存器

CMOS Dual 4-Stage Static Shift Register

Features: & Medium speed operation 12 MHz (typ.) clock rate at Vpp — Vg = 10 V ® Fully static operation 8 master-slave flip-flops plus input and output buffering # 100% tested for quiescent current at 20 V #5.V,10-V, and 15-V parametric ratings = Standardized, symmetrical

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Description CD4015BMS consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

CD4015BMS consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. \"Q\" outputs are available from each of the four stages on both registers. All register stages are D type, ma • High-Voltage Type (20V Rating) \n• Medium Speed Operation 12MHz (typ.) Clock Rate at VDD - VSS = 10V \n• Fully Static Operation \n• 8 Master-Slave Flip-Flops Plus Input and Output Buffering \n• 100% Tested For Quiescent Current at 20V \n• 5V, 10V and 15V Parametric Ratings \n• Standardized Sym;

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Features • High-Voltage Type (20V Rating) • Medium Speed Operation 12MHz (typ.) Clock Rate at VDD - VSS = 10V • Fully Static Operation • 8 Master-Slave Flip-Flops Plus Input and Output Buffering • 100 Tested For Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized S

CMOS Dual 4-Stage Static Shift Register

文件：521.58 Kbytes Page：11 Pages

CMOS Dual 4-stage Static Shift Register

文件：884.25 Kbytes Page：15 Pages

CMOS Dual 4-stage Static Shift Register

文件：884.25 Kbytes Page：15 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：串行至并行 包装：管件 描述：IC DUAL STATIC SHFT REG 16-SOIC 集成电路（IC） 移位寄存器

CMOS Dual 4-stage Static Shift Register

文件：884.25 Kbytes Page：15 Pages

CMOS Dual 4-Stage Static Shift Register

文件：521.58 Kbytes Page：11 Pages

DUAL 4-STAGE STATIC SHIFT REGISTER WITH SERIAL INPUT/PARALLEL OUTPUT

DESCRIPTION The HCC4015B (extended temperature range) and HCF4015B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micropackage. ■ MEDIUM SPEED OPERATION : 12MHz (typ.) CLOCK RATE AT VDD - VSS = 10V ■

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

SWITCHMODE??Power Rectifier

文件：68.95 Kbytes Page：4 Pages

SWITCHMODE??Power Rectifier

文件：68.95 Kbytes Page：4 Pages