CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Description CD4015BMS consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. “Q” outputs are available from each of the four stages on both registers. All register stages

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Features • High-Voltage Type (20V Rating) • Medium Speed Operation 12MHz (typ.) Clock Rate at VDD - VSS = 10V • Fully Static Operation • 8 Master-Slave Flip-Flops Plus Input and Output Buffering • 100 Tested For Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Standardized S

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

CD4015BMS consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. \"Q\" outputs are available from each of the four stages on both registers. All register stages are D type, ma • High-Voltage Type (20V Rating) \n• Medium Speed Operation 12MHz (typ.) Clock Rate at VDD - VSS = 10V \n• Fully Static Operation \n• 8 Master-Slave Flip-Flops Plus Input and Output Buffering \n• 100% Tested For Quiescent Current at 20V \n• 5V, 10V and 15V Parametric Ratings \n• Standardized Sym;

DUAL 4-STAGE STATIC SHIFT REGISTER WITH SERIAL INPUT/PARALLEL OUTPUT

DESCRIPTION The HCC4015B (extended temperature range) and HCF4015B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micropackage. ■ MEDIUM SPEED OPERATION : 12MHz (typ.) CLOCK RATE AT VDD - VSS = 10V ■

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

Dual 4-bit static shift register

DESCRIPTION The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (D), a clock input (CP), four fully buffered parallel outputs (O0 to O3) and an overriding asynchronous master reset input (MR). Information pr

SWITCHMODE??Power Rectifier

文件：68.95 Kbytes Page：4 Pages

SWITCHMODE??Power Rectifier

文件：68.95 Kbytes Page：4 Pages