8-Stage Static Shift Register

General Description The CD4014BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh and eighth stages. All outputs have equal source and sink current capabili

10 Line to 4 Line BCD Priority Encoder

Description CD40147BMS CMOS encoder features priority encoding of the inputs to ensure that only the highest order data line is encoded. Ten data input lines (0-9) are encoded to four line (8,4, 2, 1) BCD. The highest priority line is line 9. All four output lines are logic 1 (VSS) when all input

10 Line to 4 Line BCD Priority Encoder

Description\nCD40147BMS CMOS encoder features priority encoding of the inputs to ensure that only the highest order data line is encoded. Ten data input lines (0-9) are encoded to four line (8,4, 2, 1) BCD. The highest priority line is line 9. All four output lines are logic 1 (VSS) when all input l • High Voltage Type (20V Rating)\n• Encodes 10 Line to 4 Line BCD\n• Active Low Inputs and Outputs\n• 100% Tested for Quiescent Current at 20V\n• 5V, 10V and 15V Parametric Ratings\n• Maximum Input Current of 1µA at 18V Over Full Pack age Temperature Range; 100nA at 18V and +25oC\n• Noise Margin;

10-LINE TO 4-LINE BCD PRIORITY ENCODER

8-Stage Static Shift Register

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

8-Stage Static Shift Register

文件：142.54 Kbytes Page：6 Pages

丝印代码：CD40147BE；null10-Line to 4-Line BCD Priority Encoder

Features: ® Encodes 10-ine to 4-line BCD ® Active low inputs and outputs ® Standardized, symmetrical output characteristics ® 100% tested for quiescent current at 20 V ®5-V, 10-V, and 15-V parametric ratings ® Meets all requirements of JEDEC Tentative Standard No. 13A, “Standard Specifi

丝印代码：CD40147BE；null10-Line to 4-Line BCD Priority Encoder

Features: ® Encodes 10-ine to 4-line BCD ® Active low inputs and outputs ® Standardized, symmetrical output characteristics ® 100% tested for quiescent current at 20 V ®5-V, 10-V, and 15-V parametric ratings ® Meets all requirements of JEDEC Tentative Standard No. 13A, “Standard Specifi

丝印代码：CD40147BE；null10-Line to 4-Line BCD Priority Encoder

Features: ® Encodes 10-ine to 4-line BCD ® Active low inputs and outputs ® Standardized, symmetrical output characteristics ® 100% tested for quiescent current at 20 V ®5-V, 10-V, and 15-V parametric ratings ® Meets all requirements of JEDEC Tentative Standard No. 13A, “Standard Specifi

丝印代码：CD40147BM；null10-Line to 4-Line BCD Priority Encoder

Features: ® Encodes 10-ine to 4-line BCD ® Active low inputs and outputs ® Standardized, symmetrical output characteristics ® 100% tested for quiescent current at 20 V ®5-V, 10-V, and 15-V parametric ratings ® Meets all requirements of JEDEC Tentative Standard No. 13A, “Standard Specifi

丝印代码：CD40147BM；null10-Line to 4-Line BCD Priority Encoder

Features: ® Encodes 10-ine to 4-line BCD ® Active low inputs and outputs ® Standardized, symmetrical output characteristics ® 100% tested for quiescent current at 20 V ®5-V, 10-V, and 15-V parametric ratings ® Meets all requirements of JEDEC Tentative Standard No. 13A, “Standard Specifi

null10-Line to 4-Line BCD Priority Encoder

Features: ® Encodes 10-ine to 4-line BCD ® Active low inputs and outputs ® Standardized, symmetrical output characteristics ® 100% tested for quiescent current at 20 V ®5-V, 10-V, and 15-V parametric ratings ® Meets all requirements of JEDEC Tentative Standard No. 13A, “Standard Specifi

10 Line to 4 Line BCD Priority Encoder

Description CD40147BMS CMOS encoder features priority encoding of the inputs to ensure that only the highest order data line is encoded. Ten data input lines (0-9) are encoded to four line (8,4, 2, 1) BCD. The highest priority line is line 9. All four output lines are logic 1 (VSS) when all input

CMOS 8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The UTC CD4014 isa 8-stage synchronous parallel or serial input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a SERIAL data input, and individual parallel inputs to each register stage. Each register is a D-type master-slave flip-flop. Q6, Q7, and Q

8-Stage Static Shift Register

General Description The CD4014BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh and eighth stages. All outputs have equal source and sink current capabili

8-Stage Static Shift Register

General Description The CD4014BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh and eighth stages. All outputs have equal source and sink current capabili

8-Stage Static Shift Register

General Description The CD4014BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh and eighth stages. All outputs have equal source and sink current capabili

CMOS 8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The UTC CD4014 isa 8-stage synchronous parallel or serial input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a SERIAL data input, and individual parallel inputs to each register stage. Each register is a D-type master-slave flip-flop. Q6, Q7, and Q

CMOS 8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The UTC CD4014 isa 8-stage synchronous parallel or serial input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a SERIAL data input, and individual parallel inputs to each register stage. Each register is a D-type master-slave flip-flop. Q6, Q7, and Q

CMOS 8-Stage Static Shift Registers

Description CD4014BMS -Synchronous Parallel or Serial Input/Serial Output CD4021BMS -Asynchronous Parallel Input or Synchronous Serial Input/Serial Output CD4014BMS and CD4021BMS series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL

CMOS 8-Stage Static Shift Registers

Features • High Voltage Types (20V Rating) • Medium Speed Operation 12MHz (Typ.) Clock Rate at VDD-VSS = 10V • Fully Static Operation • 8 Master-Slave Flip-Flops Plus Output Buffering and Control Gating • 100 Tested for Quiescent Current at 20V • Maximum Input Current of 1A at 18V Over Fu

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

封装/外壳：16-DIP（0.300"，7.62mm） 包装：卷带（TR） 描述：IC PRIORITY ENCOD 10 X 1:4 16DIP 集成电路（IC） 信号开关，多路复用器，解码器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC PRIORITY ENCOD 1X10:4 16SOIC 集成电路（IC） 信号开关，多路复用器，解码器

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

10-LINE TO 4-LINE BCD PRIORITY ENCODER

文件：436.6 Kbytes Page：10 Pages

CMOS 8-Stage Static Shift Registers

文件：547.93 Kbytes Page：13 Pages

CMOS 8-stage Static Shift Registers

文件：1.47597 Mbytes Page：28 Pages

CMOS 8-Stage Statice Shift Registers

文件：1.45033 Mbytes Page：29 Pages

CMOS 8-stage Static Shift Registers

文件：1.47597 Mbytes Page：28 Pages

8-Stage Static Shift Register

文件：142.54 Kbytes Page：6 Pages

CMOS 8-Stage Static Shift Registers

文件：547.93 Kbytes Page：13 Pages

CMOS 8-stage Static Shift Registers

文件：1.47597 Mbytes Page：28 Pages

CMOS 8-Stage Statice Shift Registers

文件：1.45033 Mbytes Page：29 Pages

CMOS 8-Stage Statice Shift Registers

文件：1.45033 Mbytes Page：29 Pages

CMOS 8-stage Static Shift Registers

文件：1.47597 Mbytes Page：28 Pages

CMOS 8-Stage Statice Shift Registers

文件：1.45033 Mbytes Page：29 Pages

CMOS 8-stage Static Shift Registers

文件：1.47597 Mbytes Page：28 Pages

CMOS 8-Stage Static Shift Registers

文件：547.93 Kbytes Page：13 Pages

CMOS 8-Stage Static Shift Registers

文件：547.93 Kbytes Page：13 Pages

8-Stage Static Shift Register

文件：142.54 Kbytes Page：6 Pages

CMOS 8-Stage Statice Shift Registers

文件：1.45033 Mbytes Page：29 Pages

CMOS 8-stage Static Shift Registers

文件：1.47597 Mbytes Page：28 Pages

CMOS 8-Stage Static Shift Registers

文件：547.93 Kbytes Page：13 Pages

CMOS 8-Stage Statice Shift Registers

文件：1.45033 Mbytes Page：29 Pages

CMOS 8-stage Static Shift Registers

文件：1.47597 Mbytes Page：28 Pages

CMOS 8-stage Static Shift Registers

文件：1.47597 Mbytes Page：28 Pages

8-STAGE STATIC SHIFT REGISTERS

8-bit Static Shift Register

8-bit static shift register

8-bit static shift register

8-bit static shift register

8-Bit Static Shift Register

COMPLEMENTARY METAL OXIDE SILICON