8-Stage Static Shift Register

General Description The CD4014BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh and eighth stages. All outputs have equal source and sink current capabili

封装/外壳：16-DIP（0.300"，7.62mm） 功能：并行或串行至串行 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC REGISTER STAT SHIFT 8ST 16DIP 集成电路（IC） 移位寄存器

8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The HCC4014B, HCC4021B (extended temperature range) and the HCF4014B, HCF4021B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. 4014B SYNCHRONOUS PARALLEL OR SERIAL INPUT/

8-STAGE STATIC SHIFT REGISTERS

DESCRIPTION The HCC4014B, HCC4021B (extended temperature range) and the HCF4014B, HCF4021B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. 4014B SYNCHRONOUS PARALLEL OR SERIAL INPUT/

8-bit static shift register

DESCRIPTION The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (P0to P7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW to HIGH edge-triggered clock input (CP) and buffered parallel output

8-bit static shift register

DESCRIPTION The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (P0to P7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW to HIGH edge-triggered clock input (CP) and buffered parallel output

8-bit static shift register

DESCRIPTION The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight synchronous parallel inputs (P0to P7), a synchronous serial data input (DS), a synchronous parallel enable input (PE), a LOW to HIGH edge-triggered clock input (CP) and buffered parallel output