Smart Highside Power Switch (Overload protection Current limitation Short-circuit protection Thermal shutdown)

General Description N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic feedback, integrated in Smart SIPMOSâ chip on chip technology. Fully protected by embedded protection functions. Features • Overload protection • Current limitation • Shor

Smart Highside Power Switch (Overload protection Current limitation Short-circuit protection Thermal shutdown)

General Description N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic feedback, integrated in Smart SIPMOSâ chip on chip technology. Fully protected by embedded protection functions. Features ● Overload protection ● Current limitation ● Shor

CMOS compatible parallel input pins for four channels

文件：2.624 Mbytes Page：71 Pages

包装：卷带（TR） 描述：IC PWR SWITCH HISIDE PG-TSON-24 集成电路（IC） 配电开关，负载驱动器

多通道SPI高边功率控制器 | SPOC™

SPI Power Controller

文件：2.83706 Mbytes Page：69 Pages

SPI Power Controller

文件：2.83706 Mbytes Page：69 Pages

封装/外壳：24-PowerTDFN 包装：卷带（TR） 描述：IC PWR SWITCH N-CHAN 1:1 TSON-24 集成电路（IC） 配电开关，负载驱动器

CMOS compatible parallel input pins for two channels

文件：2.67288 Mbytes Page：72 Pages

SPI Power Controller

文件：2.8882 Mbytes Page：70 Pages

SPI Power Controller

文件：2.8882 Mbytes Page：70 Pages

Smart Highside Power Switch (Overload protection Current limitation Short-circuit protection Thermal shutdown)

Smart Highside Power Switch

TREK 542A

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CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b

CLOCK DIVIDER

Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide by 2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs on the chip, one being a low-skew divide b