ADC12C105 12-Bit, 95/105 MSPS A/D Converter

1FEATURES 2• 1 GHz Full Power Bandwidth • Internal Reference and Sample-and-Hold Circuit • Low Power Consumption • Data Ready Output Clock • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V Supply Operation sample• Power-Down Mode • 32-Pin WQFN Package, (5x5x0.8mm, 0.5mm Pin-Pitch)

95/105 MSPS A/D Converter

文件：1.30403 Mbytes Page：32 Pages

ADC12C105 12-Bit, 95/105 MSPS A/D Converter

1FEATURES 2• 1 GHz Full Power Bandwidth • Internal Reference and Sample-and-Hold Circuit • Low Power Consumption • Data Ready Output Clock • Clock Duty Cycle Stabilizer • Single +3.0V or +3.3V Supply Operation sample• Power-Down Mode • 32-Pin WQFN Package, (5x5x0.8mm, 0.5mm Pin-Pitch)

High Performance Quad DVGA

1FEATURES 2• OIP3: 49dBm at 200MHz • Noise Figure: 8.5dB • Voltage Gain: 26dB • 1dB Gain Steps • Enable Pins Active in SPI Mode • −3dB Bandwidth of 1400 MHz • Gain Step Accuracy: 0.2 dB • Disable Function for Each Channel • Parallel and Serial Gain Control • Low Power Mode for Power Mana

95/105 MSPS A/D Converter

文件：1.30403 Mbytes Page：32 Pages

12-Bit, 95/105 MSPS A/D Converter

文件：451.4 Kbytes Page：24 Pages

12-Bit, 95/105 MSPS A/D Converter

文件：451.4 Kbytes Page：24 Pages