Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

 SNR, 66.5 dBFS; SFDR, 86 dBc  Sample rate up to 125 Msps  11-bit pipelined ADC core  Clock input divided by 2 for less jitter contribution  Integrated input buffer  Flexible input voltage range: 1 V (p-p) to 2 V (p-p)  CMOS or LVDS DDR digital outputs  Pin compatible with the ADC

Single 11-bit ADC; 125 Msps with input buffer; CMOS or LVDS DDR digital outputs

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