Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

Integer-N Clock Translator for Wireline Communications

GENERAL DESCRIPTION The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended

Multiservice Clock Generator

GENERAL DESCRIPTION The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended

Multiservice Clock Generator

GENERAL DESCRIPTION The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended

Multiservice Clock Generator

GENERAL DESCRIPTION The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended

Multiservice Clock Generator

GENERAL DESCRIPTION The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended

Multiservice Clock Generator

GENERAL DESCRIPTION The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended

Oscillator Frequency Upconverter

GENERAL DESCRIPTION The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigma-delta (Σ-Δ) modulator (SDM) to accommodate fractional frequency synthesis. The user supplie

Oscillator Frequency Upconverter

GENERAL DESCRIPTION The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigma-delta (Σ-Δ) modulator (SDM) to accommodate fractional frequency synthesis. The user supplie

Oscillator Frequency Upconverter

GENERAL DESCRIPTION The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigma-delta (Σ-Δ) modulator (SDM) to accommodate fractional frequency synthesis. The user supplie

Oscillator Frequency Upconverter

GENERAL DESCRIPTION The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigma-delta (Σ-Δ) modulator (SDM) to accommodate fractional frequency synthesis. The user supplie

Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet

GENERAL DESCRIPTION The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two s

Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet

GENERAL DESCRIPTION The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two s

Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet

GENERAL DESCRIPTION The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two s

Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet

GENERAL DESCRIPTION The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two s

Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet

GENERAL DESCRIPTION The AD9553 is a phase-locked loop (PLL) based clock translator designed to address the needs of passive optical networks (PON) and base stations. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. The user supplies up to two s

Dual Input Multiservice

GENERAL DESCRIPTION The AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (OTN/SONET/SDH). The AD9557 generates an output clock synchronized to up to four external input references. The digital

Dual Input Multiservice

GENERAL DESCRIPTION The AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (OTN/SONET/SDH). The AD9557 generates an output clock synchronized to up to four external input references. The digital

Dual Input Multiservice

GENERAL DESCRIPTION The AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (OTN/SONET/SDH). The AD9557 generates an output clock synchronized to up to four external input references. The digital

Dual Input Multiservice

GENERAL DESCRIPTION The AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (OTN/SONET/SDH). The AD9557 generates an output clock synchronized to up to four external input references. The digital

Dual Input Multiservice

GENERAL DESCRIPTION The AD9557 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (OTN/SONET/SDH). The AD9557 generates an output clock synchronized to up to four external input references. The digital

Quad Input Multiservice Line Card Adaptive

GENERAL DESCRIPTION The AD9558 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9558 generates an output clock synchronized to up to four external input references. The digital P

封装/外壳：32-WFQFN 裸露焊盘，CSP 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC INTEGER-N TRANSLATOR 32-LFCSP 集成电路（IC） 应用特定时钟/定时

封装/外壳：32-WFQFN 裸露焊盘，CSP 包装：卷带（TR）剪切带（CT）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC INTEGER-N TRANSLATOR 32-LFCSP 集成电路（IC） 应用特定时钟/定时

Oscillator Frequency Upconverter

文件：616.18 Kbytes Page：32 Pages

Oscillator Frequency Upconverter

文件：616.18 Kbytes Page：32 Pages

Oscillator Frequency Upconverter

文件：616.18 Kbytes Page：32 Pages

Oscillator Frequency Upconverter

文件：616.18 Kbytes Page：32 Pages

Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

文件：1.06419 Mbytes Page：116 Pages

四路PLL、四通道输入、八通道输出多服务线路卡自适应时钟转换器

四路PLL、四通道输入、四通道输出多服务线路卡自适应时钟转换器

Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

文件：927.72 Kbytes Page：99 Pages

Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

文件：927.72 Kbytes Page：99 Pages

Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

文件：927.72 Kbytes Page：99 Pages

Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

文件：1.06419 Mbytes Page：116 Pages

Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

文件：1.06419 Mbytes Page：116 Pages

Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

文件：1.06419 Mbytes Page：116 Pages

Dual Input Multiservice Line Card Adaptive Clock Translator

文件：1.59924 Mbytes Page：95 Pages

Dual Input Multiservice Line Card Adaptive Clock Translator

文件：1.59924 Mbytes Page：95 Pages

Dual Input Multiservice Line Card Adaptive Clock Translator

文件：1.59924 Mbytes Page：95 Pages

Dual Input Multiservice Line Card Adaptive Clock Translator

文件：1.59924 Mbytes Page：95 Pages

Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync

文件：1.73975 Mbytes Page：105 Pages

Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync

文件：1.73975 Mbytes Page：105 Pages

Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync

文件：1.73975 Mbytes Page：105 Pages

Quad Input Multiservice Line Card Adaptive Clock Translator with Frame Sync

文件：1.73975 Mbytes Page：105 Pages

Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

文件：1.68824 Mbytes Page：120 Pages

双路PLL四通道输入多服务线路卡自适应时钟转换器

Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

文件：1.68824 Mbytes Page：120 Pages

Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

文件：1.68824 Mbytes Page：120 Pages

Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

文件：1.68824 Mbytes Page：120 Pages

SUBMINIATURE PC BOARD RELAY

FEATURES • Subminiature size for high density packaging • DIL pitch terminals • Epoxy sealed for automatic wave soldering • High sensitivity: 150 mW nominal with 84 mW pickup • Meets FCC Part 68.302 1500 V lightning surge • Meets FCC Part 68.304 1000 V dielectric • UL / CUR file E43203

SUBMINIATURE PC BOARD RELAY

[Zettler] FEATURES • Subminiature size for high density packaging • DIL pitch terminals • Epoxy sealed for automatic wave soldering • High sensitivity: 150 mW nominal with 84 mW pickup • Meets FCC Part 68.302 1500 V lightning surge • Meets FCC Part 68.304 1000 V dielectric • UL file E43203

SUBMINIATURE PC BOARD RELAY

FEATURES • Subminiature size for high density packaging • DIL pitch terminals • Epoxy sealed for automatic wave soldering • High sensitivity: 150 mW nominal with 84 mW pickup • Meets FCC Part 68.302 1500 V lightning surge • Meets FCC Part 68.304 1000 V dielectric • UL file E43203; CSA file

CONN PLUG USB3.0 MICRO USB B SLD

文件：152.96 Kbytes Page：1 Pages

CONN PLUG USB3.0 MICRO USB B SLD

文件：152.96 Kbytes Page：1 Pages