Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

AD9525旨在满足长期演进(LTE)和多载波GSM基站设计的转换器时钟要求。

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

Low Jitter Clock Generator with Eight LVPECL Outputs

GENERAL DESCRIPTION The AD9525 is designed to support converter clock requirements for long-term evolution (LTE) and multicarrier GSM base station designs. The AD9525 provides a low power, multioutput, clock distribution function with low jitter performance, along with an on-chip PLL that can be

功能：时钟发生器 包装：散装 描述：KIT EVAL FOR CRO29508 开发板，套件，编程器 评估和演示板及套件

Low Jitter Clock Generator with Eight LVPECL Outputs

文件：852.11 Kbytes Page：48 Pages

封装/外壳：48-WFQFN 裸露焊盘，CSP 包装：托盘 描述：IC CLOCK GENERATOR PLL 48-LFCSP 集成电路（IC） 时钟发生器，PLL，频率合成器

RS232, #24-25pr, SR-PVC, O/A Foil, PVC Jkt, CMG, 75Ω

Product Description Computer EIA RS-232 Cable, 24 AWG stranded (7x32) tinned copper conductors, semi-rigid PVC insulation, 25 twisted pairs, overall Beldfoil® shield (100 coverage), 24 AWG stranded tinned copper drain wire (continued), PVC jacket.

MACHINE SCREW PAN PHILLIPS 10-32

文件：130.87 Kbytes Page：1 Pages