Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path

文件：1.87998 Mbytes Page：30 Pages

封装/外壳：48-VFQFN 裸露焊盘 包装：卷带（TR） 描述：IC JITTER ATT MULT PLL 48-QFN 集成电路（IC） 应用特定时钟/定时

Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path

Dual P-Channel Enhancement Mode MOSFET

FEATURES ■ -30V, -4A, RDS(ON) = 65mΩ @VGS = -10V. RDS(ON) = 100mΩ @VGS = -4.5V. ■ Super high dense cell design for extremely low RDS(ON). ■ High power and current handing capability. ■ Surface mount Package.

Dual P-Channel Enhancement Mode Field Effect Transistor

General Description These P-Channel enhancement mode power field effect transistors are produced using Fairchilds proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. Thes

50V CERAMIC DISC

文件：14.98 Kbytes Page：1 Pages

Dual P-Channel Enhancement Mode Field Effect Transistor

文件：239.92 Kbytes Page：5 Pages

4-channel audio amplifier (SE: 1 W to 25 W; BTL: 4 W to 50 W)

文件：200.39 Kbytes Page：24 Pages