DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

Recommended Application Dual DDR zero delay buffer Features/Benefits • High performance, low jitter zero delay buffer • I2C for functional and output control • Dual bank 1-6 differential clock distribution • 2 separate feedback in & out for input to output synchronization for each bank • S

封装/外壳：48-BSSOP（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC CLK BUFF DUAL DDR 48SSOP 集成电路（IC） 应用特定时钟/定时

DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

Recommended Application Dual DDR zero delay buffer Features/Benefits • High performance, low jitter zero delay buffer • I2C for functional and output control • Dual bank 1-6 differential clock distribution • 2 separate feedback in & out for input to output synchronization for each bank • S

DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

Recommended Application Dual DDR zero delay buffer Features/Benefits • High performance, low jitter zero delay buffer • I2C for functional and output control • Dual bank 1-6 differential clock distribution • 2 separate feedback in & out for input to output synchronization for each bank • S

DUAL CHANNEL DDRII/III ZERO DELAY BUFFER

Recommended Application Dual DDR zero delay buffer Features/Benefits • High performance, low jitter zero delay buffer • I2C for functional and output control • Dual bank 1-6 differential clock distribution • 2 separate feedback in & out for input to output synchronization for each bank • S