Low Skew Dual Bank DDR I/II Fan-out Buffer

Description Output Features Dual DDR I/II fanout buffer for VIA Chipset • Low skew, fanout buffer • SMBus for functional and output control • Single bank 1-6 differential clock distribution • 1 pair of differential feedback pins for input to output synchronization • Supports up to 2 DDR DI

封装/外壳：28-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：IC FANOUT/BUFF DDR I/II 28TSSOP 集成电路（IC） 应用特定时钟/定时

Low Skew Dual Bank DDR I/II Fan-out Buffer

文件：194.3 Kbytes Page：12 Pages

Low Skew Dual Bank DDR I/II Fan-out Buffer

Description Output Features Dual DDR I/II fanout buffer for VIA Chipset • Low skew, fanout buffer • SMBus for functional and output control • Single bank 1-6 differential clock distribution • 1 pair of differential feedback pins for input to output synchronization • Supports up to 2 DDR DI

封装/外壳：28-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC FANOUT/BUFF DDR I/II 28TSSOP 集成电路（IC） 应用特定时钟/定时

Low Skew Dual Bank DDR I/II Fan-out Buffer

文件：194.3 Kbytes Page：12 Pages

Low Skew Dual Bank DDR I/II Fan-out Buffer

Description Output Features Dual DDR I/II fanout buffer for VIA Chipset • Low skew, fanout buffer • SMBus for functional and output control • Single bank 1-6 differential clock distribution • 1 pair of differential feedback pins for input to output synchronization • Supports up to 2 DDR DI

Low Skew Dual Bank DDR I/II Fan-out Buffer

Description Output Features Dual DDR I/II fanout buffer for VIA Chipset • Low skew, fanout buffer • SMBus for functional and output control • Single bank 1-6 differential clock distribution • 1 pair of differential feedback pins for input to output synchronization • Supports up to 2 DDR DI

Low Skew Dual Bank DDR I/II Fan-out Buffer

文件：194.3 Kbytes Page：12 Pages

Low Skew Dual Bank DDR I/II Fan-out Buffer

文件：194.3 Kbytes Page：12 Pages