封装/外壳：28-SSOP（0.209"，5.30mm 宽） 包装：卷带（TR） 描述：IC CLK BUF DDR 600MHZ 1CIRC 集成电路（IC） 应用特定时钟/定时

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

文件：197.4 Kbytes Page：13 Pages

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

Description Output Features DDR I/DDR II Zero Delay Clock Buffer • Low skew, low jitter PLL clock driver • Max frequency supported = 400MHz (DDRII 800) • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • Programmab

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

Description Output Features DDR I/DDR II Zero Delay Clock Buffer • Low skew, low jitter PLL clock driver • Max frequency supported = 400MHz (DDRII 800) • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • Programmab

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

文件：197.41 Kbytes Page：13 Pages

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

文件：197.41 Kbytes Page：13 Pages