Programmable Slew rate for each output

Description The 9FGV0241 is a 2-output very low power frequency generator for PCIe Gen 1, 2, 3 and 4 applications with integrated output terminations providing Zo=100. The device has 2 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off.

2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR

文件：230.26 Kbytes Page：15 Pages

2-output 1.8 V PCIe Gen1-4 Clock Generator with Zo=100 ohms

2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

2-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR

Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable Slew rate

2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR

文件：230.26 Kbytes Page：15 Pages

2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

文件：290.13 Kbytes Page：16 Pages

2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

文件：290.13 Kbytes Page：16 Pages

2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR

文件：230.26 Kbytes Page：15 Pages

2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR

文件：230.26 Kbytes Page：15 Pages

2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

文件：290.13 Kbytes Page：16 Pages

封装/外壳：24-VFQFN 裸露焊盘 包装：管件 描述：IC CLOCK GENERATOR 24VFQFPN 集成电路（IC） 应用特定时钟/定时

2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

文件：290.13 Kbytes Page：16 Pages

2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR

文件：230.26 Kbytes Page：15 Pages

封装/外壳：24-VFQFN 裸露焊盘 包装：管件 描述：IC CLOCK GENERATOR 24VFQFPN 集成电路（IC） 应用特定时钟/定时

2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

文件：290.13 Kbytes Page：16 Pages

2-OUTPUT VERY LOW POWER PCIE GEN1/2/3 CLOCK GENERATOR

文件：230.26 Kbytes Page：15 Pages