封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：TSSOP 6.50X4.40X1.00 MM, 0.65MM 集成电路（IC） 应用特定时钟/定时

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：TSSOP 6.50X4.40X1.00 MM, 0.65MM 集成电路（IC） 应用特定时钟/定时

2 and 4-Output 3.3V PCIe Gen1–5 Clock Fanout Buffers with LOS

Description The 9DBL0255/9DBL0455 are 2 and 4-output PCIe Clock fan-out buffers for PCIe Gen1–5 applications. Both parts have an open drain Loss of Signal (LOS) output to indicate the absence or presence of an input clock. The LOS circuit also implements Automatic Clock Parking (ACP) to clean