1.8V LVPECL Clock Divider

General Description The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer. The device has been designed for clock signal division and fanout in wireless base station (radio and base band), high-end computing and telecommunication equipment. The device is optimized to deliver excellent

封装/外壳：20-VFQFN 裸露焊盘 包装：托盘 描述：IC NETWORK TIMING 集成电路（IC） 时钟缓冲器，驱动器

1.8V LVPECL Clock Divider

文件：281.43 Kbytes Page：15 Pages

1.8V LVPECL Clock Divider

General Description The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer. The device has been designed for clock signal division and fanout in wireless base station (radio and base band), high-end computing and telecommunication equipment. The device is optimized to deliver excellent

Clock signal division and distribution

文件：281.43 Kbytes Page：15 Pages

1.8V LVPECL Clock Divider

文件：281.43 Kbytes Page：15 Pages

1.8V LVPECL Clock Divider

General Description The 8P73S674 is a 1.8V LVPECL Clock Divider and Fanout Buffer. The device has been designed for clock signal division and fanout in wireless base station (radio and base band), high-end computing and telecommunication equipment. The device is optimized to deliver excellent

封装/外壳：20-VFQFN 裸露焊盘 包装：托盘 描述：IC NETWORK TIMING 集成电路（IC） 时钟缓冲器，驱动器

1.8V LVPECL Clock Divider

文件：281.43 Kbytes Page：15 Pages