1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 3.3V Fanout Buffer

Features • Ten single-ended LVCMOS outputs, 7 typical output impedance • Selectable CLK0 and CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum input/output frequency: 150MHz • Output skew: 350ps (maximum) • 3.3V input, 3.3V outputs

1-to-10 Low Skew, ÷1,÷2 LVCMOS/LVTTL 3.3V Fanout Buffer

1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

Features • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance • LVPECL clock input pair • PCLK/nPCLK supports the following input levels: LVPECL, CML, SSTL • Maximum input frequency: 250MHz • Output skew: 120ps (maximum) • Part-to-part skew: 700ps (maximum) • Multiple freq

1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

Features • Ten single ended LVCMOS/LVTTL outputs, 7 typical output impedance • Selectable LVCMOS/LVTTL CLK0 and CLK1 inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum input frequency: 250MHz • Bank skew: 30ps (maximum) • Output skew: 175ps (maximum)

1-to-10 Low Skew, ÷1,÷2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

1-to-10 Low Skew,÷1,÷2 LVCMOS/LVTTL 2.5V, 3.3V Fanout Buffer

1-to-10 Low Skew, LVCMOS/LVTTL Fanout Buffer

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1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 3.3V Fanout Buffer

Features • Ten single-ended LVCMOS outputs, 7 typical output impedance • Selectable CLK0 and CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum input/output frequency: 150MHz • Output skew: 350ps (maximum) • 3.3V input, 3.3V outputs

1-to-10 Low Skew, 1, 2 LVCMOS/LVTTL 3.3V Fanout Buffer

Features • Ten single-ended LVCMOS outputs, 7 typical output impedance • Selectable CLK0 and CLK1 LVCMOS clock inputs • CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum input/output frequency: 150MHz • Output skew: 350ps (maximum) • 3.3V input, 3.3V outputs